MI_example.py revision 10917:c38f28fad4c3
16908SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26908SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36908SBrad.Beckmann@amd.com# All rights reserved. 46908SBrad.Beckmann@amd.com# 56908SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66908SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76908SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96908SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116908SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126908SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136908SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146908SBrad.Beckmann@amd.com# this software without specific prior written permission. 156908SBrad.Beckmann@amd.com# 166908SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176908SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186908SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196908SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206908SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216908SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226908SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236908SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246908SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256908SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266908SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276908SBrad.Beckmann@amd.com# 286908SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296908SBrad.Beckmann@amd.com 306908SBrad.Beckmann@amd.comimport math 316908SBrad.Beckmann@amd.comimport m5 326908SBrad.Beckmann@amd.comfrom m5.objects import * 336908SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 356908SBrad.Beckmann@amd.comfrom Ruby import send_evicts 366908SBrad.Beckmann@amd.com 376908SBrad.Beckmann@amd.com# 386908SBrad.Beckmann@amd.com# Note: the cache latency is only used by the sequencer on fast path hits 396908SBrad.Beckmann@amd.com# 407551SBrad.Beckmann@amd.comclass Cache(RubyCache): 416908SBrad.Beckmann@amd.com latency = 3 426908SBrad.Beckmann@amd.com 436908SBrad.Beckmann@amd.comdef define_options(parser): 446908SBrad.Beckmann@amd.com return 456908SBrad.Beckmann@amd.com 467551SBrad.Beckmann@amd.comdef create_system(options, full_system, system, dma_ports, ruby_system): 476908SBrad.Beckmann@amd.com 487538SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MI_example': 497539SBrad.Beckmann@amd.com panic("This script requires the MI_example protocol to be built.") 507539SBrad.Beckmann@amd.com 517539SBrad.Beckmann@amd.com cpu_sequencers = [] 527539SBrad.Beckmann@amd.com 537539SBrad.Beckmann@amd.com # 547539SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 557561SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 567561SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 577561SBrad.Beckmann@amd.com # 588929Snilay@cs.wisc.edu l1_cntrl_nodes = [] 596908SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 606908SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 616908SBrad.Beckmann@amd.com 626908SBrad.Beckmann@amd.com # 636908SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 646908SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 656908SBrad.Beckmann@amd.com # 666908SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 676908SBrad.Beckmann@amd.com 686908SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 696908SBrad.Beckmann@amd.com # 706908SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 716908SBrad.Beckmann@amd.com # Only one cache exists for this protocol, so by default use the L1D 726908SBrad.Beckmann@amd.com # config parameters. 736908SBrad.Beckmann@amd.com # 746908SBrad.Beckmann@amd.com cache = Cache(size = options.l1d_size, 756908SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 766908SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 776908SBrad.Beckmann@amd.com 786908SBrad.Beckmann@amd.com # 796908SBrad.Beckmann@amd.com # Only one unified L1 cache exists. Can cache instructions and data. 806908SBrad.Beckmann@amd.com # 816908SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 826908SBrad.Beckmann@amd.com cacheMemory = cache, 836908SBrad.Beckmann@amd.com send_evictions = send_evicts(options), 846908SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 857564SBrad.Beckmann@amd.com clk_domain=system.cpu[i].clk_domain, 868180SBrad.Beckmann@amd.com ruby_system = ruby_system) 876908SBrad.Beckmann@amd.com 888257SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 898257SBrad.Beckmann@amd.com icache = cache, 906908SBrad.Beckmann@amd.com dcache = cache, 916908SBrad.Beckmann@amd.com clk_domain=system.cpu[i].clk_domain, 926908SBrad.Beckmann@amd.com ruby_system = ruby_system) 936908SBrad.Beckmann@amd.com 946908SBrad.Beckmann@amd.com l1_cntrl.sequencer = cpu_seq 958180SBrad.Beckmann@amd.com exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 968180SBrad.Beckmann@amd.com 976908SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 988180SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 998180SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1006908SBrad.Beckmann@amd.com 1016908SBrad.Beckmann@amd.com # Connect the L1 controllers and the network 1028257SBrad.Beckmann@amd.com l1_cntrl.requestFromCache = ruby_system.network.slave 1039695Snilay@cs.wisc.edu l1_cntrl.responseFromCache = ruby_system.network.slave 1049695Snilay@cs.wisc.edu l1_cntrl.forwardToCache = ruby_system.network.master 1057564SBrad.Beckmann@amd.com l1_cntrl.responseToCache = ruby_system.network.master 1067539SBrad.Beckmann@amd.com 1077541SBrad.Beckmann@amd.com 1087541SBrad.Beckmann@amd.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1097539SBrad.Beckmann@amd.com assert(phys_mem_size % options.num_dirs == 0) 1107539SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1117539SBrad.Beckmann@amd.com 1127561SBrad.Beckmann@amd.com # Run each of the ruby memory controllers at a ratio of the frequency of 1137561SBrad.Beckmann@amd.com # the ruby system. 1148436SBrad.Beckmann@amd.com # clk_divider value is a fix to pass regression. 1158717Snilay@cs.wisc.edu ruby_system.memctrl_clk_domain = DerivedClockDomain( 1168717Snilay@cs.wisc.edu clk_domain=ruby_system.clk_domain, 1178436SBrad.Beckmann@amd.com clk_divider=3) 1187539SBrad.Beckmann@amd.com 1198322Ssteve.reinhardt@amd.com for i in xrange(options.num_dirs): 1208322Ssteve.reinhardt@amd.com dir_size = MemorySize('0B') 1218322Ssteve.reinhardt@amd.com dir_size.value = mem_module_size 1228436SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1238322Ssteve.reinhardt@amd.com directory = RubyDirectoryMemory( 1248322Ssteve.reinhardt@amd.com version = i, size = dir_size), 1258322Ssteve.reinhardt@amd.com transitions_per_cycle = options.ports, 1268322Ssteve.reinhardt@amd.com ruby_system = ruby_system) 1278845Sandreas.hansson@arm.com 1288322Ssteve.reinhardt@amd.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1299468Smalek.musleh@gmail.com dir_cntrl_nodes.append(dir_cntrl) 1306908SBrad.Beckmann@amd.com 1316908SBrad.Beckmann@amd.com # Connect the directory controllers and the network 1326908SBrad.Beckmann@amd.com dir_cntrl.requestToDir = ruby_system.network.master 1336908SBrad.Beckmann@amd.com dir_cntrl.dmaRequestToDir = ruby_system.network.master 1346908SBrad.Beckmann@amd.com 1356908SBrad.Beckmann@amd.com dir_cntrl.responseFromDir = ruby_system.network.slave 1368257SBrad.Beckmann@amd.com dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 1378257SBrad.Beckmann@amd.com dir_cntrl.forwardFromDir = ruby_system.network.slave 1388180SBrad.Beckmann@amd.com 1398180SBrad.Beckmann@amd.com 1406908SBrad.Beckmann@amd.com for i, dma_port in enumerate(dma_ports): 1416908SBrad.Beckmann@amd.com # 1426908SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1436908SBrad.Beckmann@amd.com # 1446908SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1457564SBrad.Beckmann@amd.com ruby_system = ruby_system) 1468180SBrad.Beckmann@amd.com 1476908SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1486908SBrad.Beckmann@amd.com dma_sequencer = dma_seq, 1498257SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 1509695Snilay@cs.wisc.edu ruby_system = ruby_system) 1518436SBrad.Beckmann@amd.com 1528436SBrad.Beckmann@amd.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1536908SBrad.Beckmann@amd.com exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1549468Smalek.musleh@gmail.com dma_cntrl_nodes.append(dma_cntrl) 1556908SBrad.Beckmann@amd.com 1568257SBrad.Beckmann@amd.com # Connect the directory controllers and the network 1578257SBrad.Beckmann@amd.com dma_cntrl.requestToDir = ruby_system.network.slave 1589232Sandreas.hansson@arm.com dma_cntrl.responseFromDir = ruby_system.network.master 1599232Sandreas.hansson@arm.com 1609232Sandreas.hansson@arm.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1616908SBrad.Beckmann@amd.com 1626908SBrad.Beckmann@amd.com # Create the io controller and the sequencer 1636908SBrad.Beckmann@amd.com if full_system: 1646908SBrad.Beckmann@amd.com io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 1656908SBrad.Beckmann@amd.com ruby_system._io_port = io_seq 1666908SBrad.Beckmann@amd.com io_controller = DMA_Controller(version = len(dma_ports), 1676908SBrad.Beckmann@amd.com dma_sequencer = io_seq, 1689154Spower.jg@gmail.com ruby_system = ruby_system) 1699154Spower.jg@gmail.com ruby_system.io_controller = io_controller 1706908SBrad.Beckmann@amd.com 1716908SBrad.Beckmann@amd.com # Connect the dma controller to the network 1726908SBrad.Beckmann@amd.com io_controller.responseFromDir = ruby_system.network.master 1736908SBrad.Beckmann@amd.com io_controller.requestToDir = ruby_system.network.slave 1746908SBrad.Beckmann@amd.com 1758257SBrad.Beckmann@amd.com all_cntrls = all_cntrls + [io_controller] 1766908SBrad.Beckmann@amd.com 1776908SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 1789693Snilay@cs.wisc.edu return (cpu_sequencers, dir_cntrl_nodes, topology) 1799693Snilay@cs.wisc.edu