MI_example.py revision 9841
16906SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26906SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36906SBrad.Beckmann@amd.com# All rights reserved. 46906SBrad.Beckmann@amd.com# 56906SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66906SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76906SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96906SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116906SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126906SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136906SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146906SBrad.Beckmann@amd.com# this software without specific prior written permission. 156906SBrad.Beckmann@amd.com# 166906SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176906SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186906SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196906SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206906SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216906SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226906SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236906SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246906SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256906SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266906SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276906SBrad.Beckmann@amd.com# 286906SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296906SBrad.Beckmann@amd.com 308183Snilay@cs.wisc.eduimport math 316906SBrad.Beckmann@amd.comimport m5 326906SBrad.Beckmann@amd.comfrom m5.objects import * 336906SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 356906SBrad.Beckmann@amd.com 366906SBrad.Beckmann@amd.com# 376906SBrad.Beckmann@amd.com# Note: the cache latency is only used by the sequencer on fast path hits 386906SBrad.Beckmann@amd.com# 396906SBrad.Beckmann@amd.comclass Cache(RubyCache): 406906SBrad.Beckmann@amd.com latency = 3 416906SBrad.Beckmann@amd.com 427538SBrad.Beckmann@amd.comdef define_options(parser): 437538SBrad.Beckmann@amd.com return 447538SBrad.Beckmann@amd.com 458929Snilay@cs.wisc.edudef create_system(options, system, piobus, dma_ports, ruby_system): 466906SBrad.Beckmann@amd.com 476906SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MI_example': 486906SBrad.Beckmann@amd.com panic("This script requires the MI_example protocol to be built.") 496906SBrad.Beckmann@amd.com 506906SBrad.Beckmann@amd.com cpu_sequencers = [] 516906SBrad.Beckmann@amd.com 526906SBrad.Beckmann@amd.com # 536906SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 546906SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 556906SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 566906SBrad.Beckmann@amd.com # 576906SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 586906SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 596906SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 606906SBrad.Beckmann@amd.com 616906SBrad.Beckmann@amd.com # 626906SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 636906SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 646906SBrad.Beckmann@amd.com # 658180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 668257SBrad.Beckmann@amd.com 678257SBrad.Beckmann@amd.com cntrl_count = 0 686906SBrad.Beckmann@amd.com 696906SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 706906SBrad.Beckmann@amd.com # 716906SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 726906SBrad.Beckmann@amd.com # Only one cache exists for this protocol, so by default use the L1D 736906SBrad.Beckmann@amd.com # config parameters. 746906SBrad.Beckmann@amd.com # 756906SBrad.Beckmann@amd.com cache = Cache(size = options.l1d_size, 768180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 778180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 786906SBrad.Beckmann@amd.com 796906SBrad.Beckmann@amd.com # 806906SBrad.Beckmann@amd.com # Only one unified L1 cache exists. Can cache instructions and data. 816906SBrad.Beckmann@amd.com # 828322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 838322Ssteve.reinhardt@amd.com cntrl_id = cntrl_count, 848436SBrad.Beckmann@amd.com cacheMemory = cache, 858717Snilay@cs.wisc.edu send_evictions = ( 868717Snilay@cs.wisc.edu options.cpu_type == "detailed"), 879841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 888436SBrad.Beckmann@amd.com ruby_system = ruby_system) 898322Ssteve.reinhardt@amd.com 907015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 917015SBrad.Beckmann@amd.com icache = cache, 926906SBrad.Beckmann@amd.com dcache = cache, 938436SBrad.Beckmann@amd.com ruby_system = ruby_system) 946906SBrad.Beckmann@amd.com 958322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 968322Ssteve.reinhardt@amd.com 976906SBrad.Beckmann@amd.com if piobus != None: 988845Sandreas.hansson@arm.com cpu_seq.pio_port = piobus.slave 996906SBrad.Beckmann@amd.com 1009468Smalek.musleh@gmail.com exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1016906SBrad.Beckmann@amd.com # 1026906SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1036906SBrad.Beckmann@amd.com # 1046906SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1056906SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1066906SBrad.Beckmann@amd.com 1078257SBrad.Beckmann@amd.com cntrl_count += 1 1088257SBrad.Beckmann@amd.com 1099826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1109798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1116906SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1126906SBrad.Beckmann@amd.com 1139793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1149793Sakash.bagdia@arm.com # the ruby system. 1159793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1169793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1179793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1189793Sakash.bagdia@arm.com clk_divider=3) 1199793Sakash.bagdia@arm.com 1206906SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1216906SBrad.Beckmann@amd.com # 1226906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1236906SBrad.Beckmann@amd.com # 1246906SBrad.Beckmann@amd.com 1259793Sakash.bagdia@arm.com mem_cntrl = RubyMemoryControl( 1269793Sakash.bagdia@arm.com clk_domain = ruby_system.memctrl_clk_domain, 1279793Sakash.bagdia@arm.com version = i, 1289793Sakash.bagdia@arm.com ruby_system = ruby_system) 1296906SBrad.Beckmann@amd.com 1306906SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1316906SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1326906SBrad.Beckmann@amd.com 1336906SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1348257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1356906SBrad.Beckmann@amd.com directory = \ 1367541SBrad.Beckmann@amd.com RubyDirectoryMemory( \ 1377541SBrad.Beckmann@amd.com version = i, 1387541SBrad.Beckmann@amd.com size = dir_size, 1397541SBrad.Beckmann@amd.com use_map = options.use_map, 1407541SBrad.Beckmann@amd.com map_levels = \ 1417541SBrad.Beckmann@amd.com options.map_levels), 1428436SBrad.Beckmann@amd.com memBuffer = mem_cntrl, 1439841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1448436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1456906SBrad.Beckmann@amd.com 1469468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1476906SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1486906SBrad.Beckmann@amd.com 1498257SBrad.Beckmann@amd.com cntrl_count += 1 1508257SBrad.Beckmann@amd.com 1518929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1526906SBrad.Beckmann@amd.com # 1536906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1546906SBrad.Beckmann@amd.com # 1556906SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1568477Snilay@cs.wisc.edu ruby_system = ruby_system) 1576906SBrad.Beckmann@amd.com 1586906SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1598257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1608477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1619841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1628477Snilay@cs.wisc.edu ruby_system = ruby_system) 1636906SBrad.Beckmann@amd.com 1649468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1659468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1666906SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1678257SBrad.Beckmann@amd.com cntrl_count += 1 1688257SBrad.Beckmann@amd.com 1696906SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1706906SBrad.Beckmann@amd.com 1719100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 1729100SBrad.Beckmann@amd.com 1739100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 174