MI_example.py revision 8929
16906SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26906SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36906SBrad.Beckmann@amd.com# All rights reserved. 46906SBrad.Beckmann@amd.com# 56906SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66906SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76906SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96906SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116906SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126906SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136906SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146906SBrad.Beckmann@amd.com# this software without specific prior written permission. 156906SBrad.Beckmann@amd.com# 166906SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176906SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186906SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196906SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206906SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216906SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226906SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236906SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246906SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256906SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266906SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276906SBrad.Beckmann@amd.com# 286906SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296906SBrad.Beckmann@amd.com 308183Snilay@cs.wisc.eduimport math 316906SBrad.Beckmann@amd.comimport m5 326906SBrad.Beckmann@amd.comfrom m5.objects import * 336906SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 346906SBrad.Beckmann@amd.com 356906SBrad.Beckmann@amd.com# 366906SBrad.Beckmann@amd.com# Note: the cache latency is only used by the sequencer on fast path hits 376906SBrad.Beckmann@amd.com# 386906SBrad.Beckmann@amd.comclass Cache(RubyCache): 396906SBrad.Beckmann@amd.com latency = 3 406906SBrad.Beckmann@amd.com 417538SBrad.Beckmann@amd.comdef define_options(parser): 427538SBrad.Beckmann@amd.com return 437538SBrad.Beckmann@amd.com 448929Snilay@cs.wisc.edudef create_system(options, system, piobus, dma_ports, ruby_system): 456906SBrad.Beckmann@amd.com 466906SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MI_example': 476906SBrad.Beckmann@amd.com panic("This script requires the MI_example protocol to be built.") 486906SBrad.Beckmann@amd.com 496906SBrad.Beckmann@amd.com cpu_sequencers = [] 506906SBrad.Beckmann@amd.com 516906SBrad.Beckmann@amd.com # 526906SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 536906SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 546906SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 556906SBrad.Beckmann@amd.com # 566906SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 576906SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 586906SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 596906SBrad.Beckmann@amd.com 606906SBrad.Beckmann@amd.com # 616906SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 626906SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 636906SBrad.Beckmann@amd.com # 648180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 658257SBrad.Beckmann@amd.com 668257SBrad.Beckmann@amd.com cntrl_count = 0 676906SBrad.Beckmann@amd.com 686906SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 696906SBrad.Beckmann@amd.com # 706906SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 716906SBrad.Beckmann@amd.com # Only one cache exists for this protocol, so by default use the L1D 726906SBrad.Beckmann@amd.com # config parameters. 736906SBrad.Beckmann@amd.com # 746906SBrad.Beckmann@amd.com cache = Cache(size = options.l1d_size, 758180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 768180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 776906SBrad.Beckmann@amd.com 786906SBrad.Beckmann@amd.com # 796906SBrad.Beckmann@amd.com # Only one unified L1 cache exists. Can cache instructions and data. 806906SBrad.Beckmann@amd.com # 818322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 828322Ssteve.reinhardt@amd.com cntrl_id = cntrl_count, 838436SBrad.Beckmann@amd.com cacheMemory = cache, 848717Snilay@cs.wisc.edu send_evictions = ( 858717Snilay@cs.wisc.edu options.cpu_type == "detailed"), 868436SBrad.Beckmann@amd.com ruby_system = ruby_system) 878322Ssteve.reinhardt@amd.com 887015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 897015SBrad.Beckmann@amd.com icache = cache, 906906SBrad.Beckmann@amd.com dcache = cache, 918436SBrad.Beckmann@amd.com ruby_system = ruby_system) 926906SBrad.Beckmann@amd.com 938322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 948322Ssteve.reinhardt@amd.com 956906SBrad.Beckmann@amd.com if piobus != None: 968845Sandreas.hansson@arm.com cpu_seq.pio_port = piobus.slave 976906SBrad.Beckmann@amd.com 987541SBrad.Beckmann@amd.com exec("system.l1_cntrl%d = l1_cntrl" % i) 996906SBrad.Beckmann@amd.com # 1006906SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1016906SBrad.Beckmann@amd.com # 1026906SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1036906SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1046906SBrad.Beckmann@amd.com 1058257SBrad.Beckmann@amd.com cntrl_count += 1 1068257SBrad.Beckmann@amd.com 1077541SBrad.Beckmann@amd.com phys_mem_size = long(system.physmem.range.second) - \ 1087541SBrad.Beckmann@amd.com long(system.physmem.range.first) + 1 1096906SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1106906SBrad.Beckmann@amd.com 1116906SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1126906SBrad.Beckmann@amd.com # 1136906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1146906SBrad.Beckmann@amd.com # 1156906SBrad.Beckmann@amd.com 1166906SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1176906SBrad.Beckmann@amd.com 1186906SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1196906SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1206906SBrad.Beckmann@amd.com 1216906SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1228257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1236906SBrad.Beckmann@amd.com directory = \ 1247541SBrad.Beckmann@amd.com RubyDirectoryMemory( \ 1257541SBrad.Beckmann@amd.com version = i, 1267541SBrad.Beckmann@amd.com size = dir_size, 1277541SBrad.Beckmann@amd.com use_map = options.use_map, 1287541SBrad.Beckmann@amd.com map_levels = \ 1297541SBrad.Beckmann@amd.com options.map_levels), 1308436SBrad.Beckmann@amd.com memBuffer = mem_cntrl, 1318436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1326906SBrad.Beckmann@amd.com 1337541SBrad.Beckmann@amd.com exec("system.dir_cntrl%d = dir_cntrl" % i) 1346906SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1356906SBrad.Beckmann@amd.com 1368257SBrad.Beckmann@amd.com cntrl_count += 1 1378257SBrad.Beckmann@amd.com 1388929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1396906SBrad.Beckmann@amd.com # 1406906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1416906SBrad.Beckmann@amd.com # 1426906SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1438477Snilay@cs.wisc.edu ruby_system = ruby_system) 1446906SBrad.Beckmann@amd.com 1456906SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1468257SBrad.Beckmann@amd.com cntrl_id = cntrl_count, 1478477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1488477Snilay@cs.wisc.edu ruby_system = ruby_system) 1496906SBrad.Beckmann@amd.com 1507541SBrad.Beckmann@amd.com exec("system.dma_cntrl%d = dma_cntrl" % i) 1518929Snilay@cs.wisc.edu exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1526906SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1538257SBrad.Beckmann@amd.com cntrl_count += 1 1548257SBrad.Beckmann@amd.com 1556906SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1566906SBrad.Beckmann@amd.com 1576906SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 158