MI_example.py revision 7541
12155SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22155SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 32155SN/A# All rights reserved. 42155SN/A# 52155SN/A# Redistribution and use in source and binary forms, with or without 62155SN/A# modification, are permitted provided that the following conditions are 72155SN/A# met: redistributions of source code must retain the above copyright 82155SN/A# notice, this list of conditions and the following disclaimer; 92155SN/A# redistributions in binary form must reproduce the above copyright 102155SN/A# notice, this list of conditions and the following disclaimer in the 112155SN/A# documentation and/or other materials provided with the distribution; 122155SN/A# neither the name of the copyright holders nor the names of its 132155SN/A# contributors may be used to endorse or promote products derived from 142155SN/A# this software without specific prior written permission. 152155SN/A# 162155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272155SN/A# 282665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 292665Ssaidi@eecs.umich.edu 302155SN/Aimport m5 314202Sbinkertn@umich.edufrom m5.objects import * 322155SN/Afrom m5.defines import buildEnv 332178SN/A 342178SN/A# 352178SN/A# Note: the cache latency is only used by the sequencer on fast path hits 362178SN/A# 372178SN/Aclass Cache(RubyCache): 382178SN/A latency = 3 392178SN/A 402178SN/Adef define_options(parser): 412178SN/A return 422178SN/A 432178SN/Adef create_system(options, system, piobus, dma_devices): 442155SN/A 455865Sksewell@umich.edu if buildEnv['PROTOCOL'] != 'MI_example': 466181Sksewell@umich.edu panic("This script requires the MI_example protocol to be built.") 476181Sksewell@umich.edu 485865Sksewell@umich.edu cpu_sequencers = [] 493918Ssaidi@eecs.umich.edu 505865Sksewell@umich.edu # 512623SN/A # The ruby network creation expects the list of nodes in the system to be 523918Ssaidi@eecs.umich.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 532155SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 542155SN/A # 552292SN/A l1_cntrl_nodes = [] 566181Sksewell@umich.edu dir_cntrl_nodes = [] 576181Sksewell@umich.edu dma_cntrl_nodes = [] 583918Ssaidi@eecs.umich.edu 592292SN/A # 602292SN/A # Must create the individual controllers before the network to ensure the 612292SN/A # controller constructors are called before the network constructor 623918Ssaidi@eecs.umich.edu # 632292SN/A 642292SN/A for i in xrange(options.num_cpus): 652766Sktlim@umich.edu # 662766Sktlim@umich.edu # First create the Ruby objects associated with this cpu 672766Sktlim@umich.edu # Only one cache exists for this protocol, so by default use the L1D 682921Sktlim@umich.edu # config parameters. 692921Sktlim@umich.edu # 702766Sktlim@umich.edu cache = Cache(size = options.l1d_size, 712766Sktlim@umich.edu assoc = options.l1d_assoc) 725529Snate@binkert.org 732766Sktlim@umich.edu # 744762Snate@binkert.org # Only one unified L1 cache exists. Can cache instructions and data. 752155SN/A # 762155SN/A cpu_seq = RubySequencer(version = i, 772155SN/A icache = cache, 782155SN/A dcache = cache, 792155SN/A physMemPort = system.physmem.port, 802155SN/A physmem = system.physmem) 812766Sktlim@umich.edu 822155SN/A if piobus != None: 835865Sksewell@umich.edu cpu_seq.pio_port = piobus.port 842155SN/A 852155SN/A l1_cntrl = L1Cache_Controller(version = i, 862155SN/A sequencer = cpu_seq, 872155SN/A cacheMemory = cache) 882178SN/A 892178SN/A exec("system.l1_cntrl%d = l1_cntrl" % i) 902178SN/A # 912766Sktlim@umich.edu # Add controllers and sequencers to the appropriate lists 922178SN/A # 932178SN/A cpu_sequencers.append(cpu_seq) 946994Snate@binkert.org l1_cntrl_nodes.append(l1_cntrl) 952178SN/A 962766Sktlim@umich.edu phys_mem_size = long(system.physmem.range.second) - \ 972766Sktlim@umich.edu long(system.physmem.range.first) + 1 982766Sktlim@umich.edu mem_module_size = phys_mem_size / options.num_dirs 992788Sktlim@umich.edu 1002178SN/A for i in xrange(options.num_dirs): 1012733Sktlim@umich.edu # 1022733Sktlim@umich.edu # Create the Ruby objects associated with the directory controller 1032817Sksewell@umich.edu # 1042733Sktlim@umich.edu 1054486Sbinkertn@umich.edu mem_cntrl = RubyMemoryControl(version = i) 1064486Sbinkertn@umich.edu 1074776Sgblack@eecs.umich.edu dir_size = MemorySize('0B') 1084776Sgblack@eecs.umich.edu dir_size.value = mem_module_size 1096365Sgblack@eecs.umich.edu 1104486Sbinkertn@umich.edu dir_cntrl = Directory_Controller(version = i, 1114202Sbinkertn@umich.edu directory = \ 1124202Sbinkertn@umich.edu RubyDirectoryMemory( \ 1134202Sbinkertn@umich.edu version = i, 1144202Sbinkertn@umich.edu size = dir_size, 1154202Sbinkertn@umich.edu use_map = options.use_map, 1164776Sgblack@eecs.umich.edu map_levels = \ 1176365Sgblack@eecs.umich.edu options.map_levels), 1184202Sbinkertn@umich.edu memBuffer = mem_cntrl) 1194202Sbinkertn@umich.edu 1204202Sbinkertn@umich.edu exec("system.dir_cntrl%d = dir_cntrl" % i) 1214202Sbinkertn@umich.edu dir_cntrl_nodes.append(dir_cntrl) 1225217Ssaidi@eecs.umich.edu 1234202Sbinkertn@umich.edu for i, dma_device in enumerate(dma_devices): 1242155SN/A # 1254202Sbinkertn@umich.edu # Create the Ruby objects associated with the dma controller 1264486Sbinkertn@umich.edu # 1274486Sbinkertn@umich.edu dma_seq = DMASequencer(version = i, 1284202Sbinkertn@umich.edu physMemPort = system.physmem.port, 1294202Sbinkertn@umich.edu physmem = system.physmem) 1302821Sktlim@umich.edu 1314776Sgblack@eecs.umich.edu dma_cntrl = DMA_Controller(version = i, 1324776Sgblack@eecs.umich.edu dma_sequencer = dma_seq) 1334776Sgblack@eecs.umich.edu 1344776Sgblack@eecs.umich.edu exec("system.dma_cntrl%d = dma_cntrl" % i) 1352766Sktlim@umich.edu dma_cntrl.dma_sequencer.port = dma_device.dma 1364202Sbinkertn@umich.edu dma_cntrl_nodes.append(dma_cntrl) 1375192Ssaidi@eecs.umich.edu 1382733Sktlim@umich.edu all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1392733Sktlim@umich.edu 1402733Sktlim@umich.edu return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 1412733Sktlim@umich.edu