MI_example.py revision 6906
16906SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26906SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36906SBrad.Beckmann@amd.com# All rights reserved. 46906SBrad.Beckmann@amd.com# 56906SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66906SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76906SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96906SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116906SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126906SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136906SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146906SBrad.Beckmann@amd.com# this software without specific prior written permission. 156906SBrad.Beckmann@amd.com# 166906SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176906SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186906SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196906SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206906SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216906SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226906SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236906SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246906SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256906SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266906SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276906SBrad.Beckmann@amd.com# 286906SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296906SBrad.Beckmann@amd.com 306906SBrad.Beckmann@amd.comimport m5 316906SBrad.Beckmann@amd.comfrom m5.objects import * 326906SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 336906SBrad.Beckmann@amd.comfrom m5.util import addToPath 346906SBrad.Beckmann@amd.com 356906SBrad.Beckmann@amd.com# 366906SBrad.Beckmann@amd.com# Note: the cache latency is only used by the sequencer on fast path hits 376906SBrad.Beckmann@amd.com# 386906SBrad.Beckmann@amd.comclass Cache(RubyCache): 396906SBrad.Beckmann@amd.com latency = 3 406906SBrad.Beckmann@amd.com 416906SBrad.Beckmann@amd.comdef create_system(options, phys_mem, piobus, dma_devices): 426906SBrad.Beckmann@amd.com 436906SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MI_example': 446906SBrad.Beckmann@amd.com panic("This script requires the MI_example protocol to be built.") 456906SBrad.Beckmann@amd.com 466906SBrad.Beckmann@amd.com cpu_sequencers = [] 476906SBrad.Beckmann@amd.com 486906SBrad.Beckmann@amd.com # 496906SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 506906SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 516906SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 526906SBrad.Beckmann@amd.com # 536906SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 546906SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 556906SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 566906SBrad.Beckmann@amd.com 576906SBrad.Beckmann@amd.com # 586906SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 596906SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 606906SBrad.Beckmann@amd.com # 616906SBrad.Beckmann@amd.com 626906SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 636906SBrad.Beckmann@amd.com # 646906SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 656906SBrad.Beckmann@amd.com # Only one cache exists for this protocol, so by default use the L1D 666906SBrad.Beckmann@amd.com # config parameters. 676906SBrad.Beckmann@amd.com # 686906SBrad.Beckmann@amd.com cache = Cache(size = options.l1d_size, 696906SBrad.Beckmann@amd.com assoc = options.l1d_assoc) 706906SBrad.Beckmann@amd.com 716906SBrad.Beckmann@amd.com # 726906SBrad.Beckmann@amd.com # Only one unified L1 cache exists. Can cache instructions and data. 736906SBrad.Beckmann@amd.com # 746906SBrad.Beckmann@amd.com cpu_seq = RubySequencer(icache = cache, 756906SBrad.Beckmann@amd.com dcache = cache, 766906SBrad.Beckmann@amd.com physMemPort = phys_mem.port, 776906SBrad.Beckmann@amd.com physmem = phys_mem) 786906SBrad.Beckmann@amd.com 796906SBrad.Beckmann@amd.com if piobus != None: 806906SBrad.Beckmann@amd.com cpu_seq.pio_port = piobus.port 816906SBrad.Beckmann@amd.com 826906SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 836906SBrad.Beckmann@amd.com sequencer = cpu_seq, 846906SBrad.Beckmann@amd.com cacheMemory = cache) 856906SBrad.Beckmann@amd.com # 866906SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 876906SBrad.Beckmann@amd.com # 886906SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 896906SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 906906SBrad.Beckmann@amd.com 916906SBrad.Beckmann@amd.com phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 926906SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 936906SBrad.Beckmann@amd.com 946906SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 956906SBrad.Beckmann@amd.com # 966906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 976906SBrad.Beckmann@amd.com # 986906SBrad.Beckmann@amd.com 996906SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1006906SBrad.Beckmann@amd.com 1016906SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1026906SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1036906SBrad.Beckmann@amd.com 1046906SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1056906SBrad.Beckmann@amd.com directory = \ 1066906SBrad.Beckmann@amd.com RubyDirectoryMemory(version = i, 1076906SBrad.Beckmann@amd.com size = dir_size), 1086906SBrad.Beckmann@amd.com memBuffer = mem_cntrl) 1096906SBrad.Beckmann@amd.com 1106906SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1116906SBrad.Beckmann@amd.com 1126906SBrad.Beckmann@amd.com for i, dma_device in enumerate(dma_devices): 1136906SBrad.Beckmann@amd.com # 1146906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1156906SBrad.Beckmann@amd.com # 1166906SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1176906SBrad.Beckmann@amd.com physMemPort = phys_mem.port, 1186906SBrad.Beckmann@amd.com physmem = phys_mem) 1196906SBrad.Beckmann@amd.com 1206906SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1216906SBrad.Beckmann@amd.com dma_sequencer = dma_seq) 1226906SBrad.Beckmann@amd.com 1236906SBrad.Beckmann@amd.com dma_cntrl.dma_sequencer.port = dma_device.dma 1246906SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1256906SBrad.Beckmann@amd.com 1266906SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1276906SBrad.Beckmann@amd.com 1286906SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 129