MI_example.py revision 11266
16906SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26906SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36906SBrad.Beckmann@amd.com# All rights reserved. 46906SBrad.Beckmann@amd.com# 56906SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66906SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76906SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96906SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116906SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126906SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136906SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146906SBrad.Beckmann@amd.com# this software without specific prior written permission. 156906SBrad.Beckmann@amd.com# 166906SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176906SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186906SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196906SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206906SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216906SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226906SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236906SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246906SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256906SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266906SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276906SBrad.Beckmann@amd.com# 286906SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296906SBrad.Beckmann@amd.com 308183Snilay@cs.wisc.eduimport math 316906SBrad.Beckmann@amd.comimport m5 326906SBrad.Beckmann@amd.comfrom m5.objects import * 336906SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366906SBrad.Beckmann@amd.com 376906SBrad.Beckmann@amd.com# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396906SBrad.Beckmann@amd.com# 4011052Sandreas.hansson@arm.comclass L1Cache(RubyCache): pass 416906SBrad.Beckmann@amd.com 427538SBrad.Beckmann@amd.comdef define_options(parser): 437538SBrad.Beckmann@amd.com return 447538SBrad.Beckmann@amd.com 4510519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 4610917Sbrandon.potter@amd.com 476906SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MI_example': 486906SBrad.Beckmann@amd.com panic("This script requires the MI_example protocol to be built.") 496906SBrad.Beckmann@amd.com 506906SBrad.Beckmann@amd.com cpu_sequencers = [] 5110917Sbrandon.potter@amd.com 526906SBrad.Beckmann@amd.com # 536906SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 546906SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 556906SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 566906SBrad.Beckmann@amd.com # 576906SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 586906SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 596906SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 606906SBrad.Beckmann@amd.com 616906SBrad.Beckmann@amd.com # 626906SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 636906SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 646906SBrad.Beckmann@amd.com # 658180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 668257SBrad.Beckmann@amd.com 676906SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 686906SBrad.Beckmann@amd.com # 696906SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 706906SBrad.Beckmann@amd.com # Only one cache exists for this protocol, so by default use the L1D 716906SBrad.Beckmann@amd.com # config parameters. 726906SBrad.Beckmann@amd.com # 7311052Sandreas.hansson@arm.com cache = L1Cache(size = options.l1d_size, 7411052Sandreas.hansson@arm.com assoc = options.l1d_assoc, 7511052Sandreas.hansson@arm.com start_index_bit = block_size_bits) 766906SBrad.Beckmann@amd.com 778322Ssteve.reinhardt@amd.com 7811266SBrad.Beckmann@amd.com # the ruby random tester reuses num_cpus to specify the 7911266SBrad.Beckmann@amd.com # number of cpu ports connected to the tester object, which 8011266SBrad.Beckmann@amd.com # is stored in system.cpu. because there is only ever one 8111266SBrad.Beckmann@amd.com # tester object, num_cpus is not necessarily equal to the 8211266SBrad.Beckmann@amd.com # size of system.cpu; therefore if len(system.cpu) == 1 8311266SBrad.Beckmann@amd.com # we use system.cpu[0] to set the clk_domain, thereby ensuring 8411266SBrad.Beckmann@amd.com # we don't index off the end of the cpu list. 8511266SBrad.Beckmann@amd.com if len(system.cpu) == 1: 8611266SBrad.Beckmann@amd.com clk_domain = system.cpu[0].clk_domain 8711266SBrad.Beckmann@amd.com else: 8811266SBrad.Beckmann@amd.com clk_domain = system.cpu[i].clk_domain 8911266SBrad.Beckmann@amd.com 9011266SBrad.Beckmann@amd.com # Only one unified L1 cache exists. Can cache instructions and data. 9111266SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache, 9211266SBrad.Beckmann@amd.com send_evictions=send_evicts(options), 9311266SBrad.Beckmann@amd.com transitions_per_cycle=options.ports, 9411266SBrad.Beckmann@amd.com clk_domain=clk_domain, 9511266SBrad.Beckmann@amd.com ruby_system=ruby_system) 9611266SBrad.Beckmann@amd.com 9711266SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache, 9811266SBrad.Beckmann@amd.com clk_domain=clk_domain, ruby_system=ruby_system) 996906SBrad.Beckmann@amd.com 1008322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 10110116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1028322Ssteve.reinhardt@amd.com 1036906SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1046906SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1056906SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1066906SBrad.Beckmann@amd.com 10710311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 10811022Sjthestness@gmail.com l1_cntrl.mandatoryQueue = MessageBuffer() 10911022Sjthestness@gmail.com l1_cntrl.requestFromCache = MessageBuffer(ordered = True) 11011022Sjthestness@gmail.com l1_cntrl.requestFromCache.master = ruby_system.network.slave 11111022Sjthestness@gmail.com l1_cntrl.responseFromCache = MessageBuffer(ordered = True) 11211022Sjthestness@gmail.com l1_cntrl.responseFromCache.master = ruby_system.network.slave 11311022Sjthestness@gmail.com l1_cntrl.forwardToCache = MessageBuffer(ordered = True) 11411022Sjthestness@gmail.com l1_cntrl.forwardToCache.slave = ruby_system.network.master 11511022Sjthestness@gmail.com l1_cntrl.responseToCache = MessageBuffer(ordered = True) 11611022Sjthestness@gmail.com l1_cntrl.responseToCache.slave = ruby_system.network.master 11710311Snilay@cs.wisc.edu 1189826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1199798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1206906SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1216906SBrad.Beckmann@amd.com 1229793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1239793Sakash.bagdia@arm.com # the ruby system. 1249793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1259793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1269793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1279793Sakash.bagdia@arm.com clk_divider=3) 1289793Sakash.bagdia@arm.com 1296906SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1306906SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1316906SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1326906SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 13310524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 13410524Snilay@cs.wisc.edu version = i, size = dir_size), 1359841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1368436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1376906SBrad.Beckmann@amd.com 1389468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1396906SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1406906SBrad.Beckmann@amd.com 14110311Snilay@cs.wisc.edu # Connect the directory controllers and the network 14211022Sjthestness@gmail.com dir_cntrl.requestToDir = MessageBuffer(ordered = True) 14311022Sjthestness@gmail.com dir_cntrl.requestToDir.slave = ruby_system.network.master 14411022Sjthestness@gmail.com dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) 14511022Sjthestness@gmail.com dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master 14610311Snilay@cs.wisc.edu 14711022Sjthestness@gmail.com dir_cntrl.responseFromDir = MessageBuffer() 14811022Sjthestness@gmail.com dir_cntrl.responseFromDir.master = ruby_system.network.slave 14911022Sjthestness@gmail.com dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) 15011022Sjthestness@gmail.com dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave 15111022Sjthestness@gmail.com dir_cntrl.forwardFromDir = MessageBuffer() 15211022Sjthestness@gmail.com dir_cntrl.forwardFromDir.master = ruby_system.network.slave 15311022Sjthestness@gmail.com dir_cntrl.responseFromMemory = MessageBuffer() 15410311Snilay@cs.wisc.edu 15510311Snilay@cs.wisc.edu 1568929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1576906SBrad.Beckmann@amd.com # 1586906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1596906SBrad.Beckmann@amd.com # 1606906SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1618477Snilay@cs.wisc.edu ruby_system = ruby_system) 16210917Sbrandon.potter@amd.com 1636906SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1648477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1659841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1668477Snilay@cs.wisc.edu ruby_system = ruby_system) 1676906SBrad.Beckmann@amd.com 1689468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1699468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1706906SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1718257SBrad.Beckmann@amd.com 17210311Snilay@cs.wisc.edu # Connect the directory controllers and the network 17311022Sjthestness@gmail.com dma_cntrl.mandatoryQueue = MessageBuffer() 17411022Sjthestness@gmail.com dma_cntrl.requestToDir = MessageBuffer() 17511022Sjthestness@gmail.com dma_cntrl.requestToDir.master = ruby_system.network.slave 17611022Sjthestness@gmail.com dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 17711022Sjthestness@gmail.com dma_cntrl.responseFromDir.slave = ruby_system.network.master 17810311Snilay@cs.wisc.edu 17910519Snilay@cs.wisc.edu all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 18010311Snilay@cs.wisc.edu 18110519Snilay@cs.wisc.edu # Create the io controller and the sequencer 18210519Snilay@cs.wisc.edu if full_system: 18310519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 18410519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 18510519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 18610519Snilay@cs.wisc.edu dma_sequencer = io_seq, 18710519Snilay@cs.wisc.edu ruby_system = ruby_system) 18810519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 18910519Snilay@cs.wisc.edu 19010519Snilay@cs.wisc.edu # Connect the dma controller to the network 19111022Sjthestness@gmail.com io_controller.mandatoryQueue = MessageBuffer() 19211022Sjthestness@gmail.com io_controller.requestToDir = MessageBuffer() 19311022Sjthestness@gmail.com io_controller.requestToDir.master = ruby_system.network.slave 19411022Sjthestness@gmail.com io_controller.responseFromDir = MessageBuffer(ordered = True) 19511022Sjthestness@gmail.com io_controller.responseFromDir.slave = ruby_system.network.master 19610519Snilay@cs.wisc.edu 19710519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 19810519Snilay@cs.wisc.edu 19911065Snilay@cs.wisc.edu ruby_system.network.number_of_virtual_networks = 5 2009100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 2019100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 202