MI_example.py revision 11019
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35from Ruby import send_evicts 36 37# 38# Declare caches used by the protocol 39# 40class Cache(RubyCache): pass 41 42def define_options(parser): 43 return 44 45def create_system(options, full_system, system, dma_ports, ruby_system): 46 47 if buildEnv['PROTOCOL'] != 'MI_example': 48 panic("This script requires the MI_example protocol to be built.") 49 50 cpu_sequencers = [] 51 52 # 53 # The ruby network creation expects the list of nodes in the system to be 54 # consistent with the NetDest list. Therefore the l1 controller nodes must be 55 # listed before the directory nodes and directory nodes before dma nodes, etc. 56 # 57 l1_cntrl_nodes = [] 58 dir_cntrl_nodes = [] 59 dma_cntrl_nodes = [] 60 61 # 62 # Must create the individual controllers before the network to ensure the 63 # controller constructors are called before the network constructor 64 # 65 block_size_bits = int(math.log(options.cacheline_size, 2)) 66 67 for i in xrange(options.num_cpus): 68 # 69 # First create the Ruby objects associated with this cpu 70 # Only one cache exists for this protocol, so by default use the L1D 71 # config parameters. 72 # 73 cache = Cache(size = options.l1d_size, 74 assoc = options.l1d_assoc, 75 start_index_bit = block_size_bits) 76 77 # 78 # Only one unified L1 cache exists. Can cache instructions and data. 79 # 80 l1_cntrl = L1Cache_Controller(version = i, 81 cacheMemory = cache, 82 send_evictions = send_evicts(options), 83 transitions_per_cycle = options.ports, 84 clk_domain=system.cpu[i].clk_domain, 85 ruby_system = ruby_system) 86 87 cpu_seq = RubySequencer(version = i, 88 icache = cache, 89 dcache = cache, 90 clk_domain=system.cpu[i].clk_domain, 91 ruby_system = ruby_system) 92 93 l1_cntrl.sequencer = cpu_seq 94 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 95 96 # Add controllers and sequencers to the appropriate lists 97 cpu_sequencers.append(cpu_seq) 98 l1_cntrl_nodes.append(l1_cntrl) 99 100 # Connect the L1 controllers and the network 101 l1_cntrl.requestFromCache = ruby_system.network.slave 102 l1_cntrl.responseFromCache = ruby_system.network.slave 103 l1_cntrl.forwardToCache = ruby_system.network.master 104 l1_cntrl.responseToCache = ruby_system.network.master 105 106 107 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 108 assert(phys_mem_size % options.num_dirs == 0) 109 mem_module_size = phys_mem_size / options.num_dirs 110 111 # Run each of the ruby memory controllers at a ratio of the frequency of 112 # the ruby system. 113 # clk_divider value is a fix to pass regression. 114 ruby_system.memctrl_clk_domain = DerivedClockDomain( 115 clk_domain=ruby_system.clk_domain, 116 clk_divider=3) 117 118 for i in xrange(options.num_dirs): 119 dir_size = MemorySize('0B') 120 dir_size.value = mem_module_size 121 dir_cntrl = Directory_Controller(version = i, 122 directory = RubyDirectoryMemory( 123 version = i, size = dir_size), 124 transitions_per_cycle = options.ports, 125 ruby_system = ruby_system) 126 127 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 128 dir_cntrl_nodes.append(dir_cntrl) 129 130 # Connect the directory controllers and the network 131 dir_cntrl.requestToDir = ruby_system.network.master 132 dir_cntrl.dmaRequestToDir = ruby_system.network.master 133 134 dir_cntrl.responseFromDir = ruby_system.network.slave 135 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 136 dir_cntrl.forwardFromDir = ruby_system.network.slave 137 138 139 for i, dma_port in enumerate(dma_ports): 140 # 141 # Create the Ruby objects associated with the dma controller 142 # 143 dma_seq = DMASequencer(version = i, 144 ruby_system = ruby_system) 145 146 dma_cntrl = DMA_Controller(version = i, 147 dma_sequencer = dma_seq, 148 transitions_per_cycle = options.ports, 149 ruby_system = ruby_system) 150 151 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 152 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 153 dma_cntrl_nodes.append(dma_cntrl) 154 155 # Connect the directory controllers and the network 156 dma_cntrl.requestToDir = ruby_system.network.slave 157 dma_cntrl.responseFromDir = ruby_system.network.master 158 159 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 160 161 # Create the io controller and the sequencer 162 if full_system: 163 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 164 ruby_system._io_port = io_seq 165 io_controller = DMA_Controller(version = len(dma_ports), 166 dma_sequencer = io_seq, 167 ruby_system = ruby_system) 168 ruby_system.io_controller = io_controller 169 170 # Connect the dma controller to the network 171 io_controller.responseFromDir = ruby_system.network.master 172 io_controller.requestToDir = ruby_system.network.slave 173 174 all_cntrls = all_cntrls + [io_controller] 175 176 topology = create_topology(all_cntrls, options) 177 return (cpu_sequencers, dir_cntrl_nodes, topology) 178