MI_example.py revision 10917
16906SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26906SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36906SBrad.Beckmann@amd.com# All rights reserved. 46906SBrad.Beckmann@amd.com# 56906SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66906SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76906SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96906SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106906SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116906SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126906SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136906SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146906SBrad.Beckmann@amd.com# this software without specific prior written permission. 156906SBrad.Beckmann@amd.com# 166906SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176906SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186906SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196906SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206906SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216906SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226906SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236906SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246906SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256906SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266906SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276906SBrad.Beckmann@amd.com# 286906SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296906SBrad.Beckmann@amd.com 308183Snilay@cs.wisc.eduimport math 316906SBrad.Beckmann@amd.comimport m5 326906SBrad.Beckmann@amd.comfrom m5.objects import * 336906SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366906SBrad.Beckmann@amd.com 376906SBrad.Beckmann@amd.com# 386906SBrad.Beckmann@amd.com# Note: the cache latency is only used by the sequencer on fast path hits 396906SBrad.Beckmann@amd.com# 406906SBrad.Beckmann@amd.comclass Cache(RubyCache): 416906SBrad.Beckmann@amd.com latency = 3 426906SBrad.Beckmann@amd.com 437538SBrad.Beckmann@amd.comdef define_options(parser): 447538SBrad.Beckmann@amd.com return 457538SBrad.Beckmann@amd.com 4610519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 4710917Sbrandon.potter@amd.com 486906SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MI_example': 496906SBrad.Beckmann@amd.com panic("This script requires the MI_example protocol to be built.") 506906SBrad.Beckmann@amd.com 516906SBrad.Beckmann@amd.com cpu_sequencers = [] 5210917Sbrandon.potter@amd.com 536906SBrad.Beckmann@amd.com # 546906SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 556906SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 566906SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 576906SBrad.Beckmann@amd.com # 586906SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 596906SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 606906SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 616906SBrad.Beckmann@amd.com 626906SBrad.Beckmann@amd.com # 636906SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 646906SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 656906SBrad.Beckmann@amd.com # 668180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 678257SBrad.Beckmann@amd.com 686906SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 696906SBrad.Beckmann@amd.com # 706906SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 716906SBrad.Beckmann@amd.com # Only one cache exists for this protocol, so by default use the L1D 726906SBrad.Beckmann@amd.com # config parameters. 736906SBrad.Beckmann@amd.com # 746906SBrad.Beckmann@amd.com cache = Cache(size = options.l1d_size, 758180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 768180SBrad.Beckmann@amd.com start_index_bit = block_size_bits) 776906SBrad.Beckmann@amd.com 786906SBrad.Beckmann@amd.com # 796906SBrad.Beckmann@amd.com # Only one unified L1 cache exists. Can cache instructions and data. 806906SBrad.Beckmann@amd.com # 818322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 828436SBrad.Beckmann@amd.com cacheMemory = cache, 8310529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 849841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 8510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 868436SBrad.Beckmann@amd.com ruby_system = ruby_system) 878322Ssteve.reinhardt@amd.com 887015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 897015SBrad.Beckmann@amd.com icache = cache, 906906SBrad.Beckmann@amd.com dcache = cache, 9110300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 928436SBrad.Beckmann@amd.com ruby_system = ruby_system) 936906SBrad.Beckmann@amd.com 948322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 9510116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 968322Ssteve.reinhardt@amd.com 976906SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 986906SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 996906SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1006906SBrad.Beckmann@amd.com 10110311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 10210311Snilay@cs.wisc.edu l1_cntrl.requestFromCache = ruby_system.network.slave 10310311Snilay@cs.wisc.edu l1_cntrl.responseFromCache = ruby_system.network.slave 10410311Snilay@cs.wisc.edu l1_cntrl.forwardToCache = ruby_system.network.master 10510311Snilay@cs.wisc.edu l1_cntrl.responseToCache = ruby_system.network.master 10610311Snilay@cs.wisc.edu 10710311Snilay@cs.wisc.edu 1089826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1099798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1106906SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1116906SBrad.Beckmann@amd.com 1129793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1139793Sakash.bagdia@arm.com # the ruby system. 1149793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1159793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1169793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1179793Sakash.bagdia@arm.com clk_divider=3) 1189793Sakash.bagdia@arm.com 1196906SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1206906SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1216906SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1226906SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 12310524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 12410524Snilay@cs.wisc.edu version = i, size = dir_size), 1259841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1268436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1276906SBrad.Beckmann@amd.com 1289468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1296906SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1306906SBrad.Beckmann@amd.com 13110311Snilay@cs.wisc.edu # Connect the directory controllers and the network 13210311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 13310311Snilay@cs.wisc.edu dir_cntrl.dmaRequestToDir = ruby_system.network.master 13410311Snilay@cs.wisc.edu 13510311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 13610311Snilay@cs.wisc.edu dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 13710311Snilay@cs.wisc.edu dir_cntrl.forwardFromDir = ruby_system.network.slave 13810311Snilay@cs.wisc.edu 13910311Snilay@cs.wisc.edu 1408929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1416906SBrad.Beckmann@amd.com # 1426906SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1436906SBrad.Beckmann@amd.com # 1446906SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1458477Snilay@cs.wisc.edu ruby_system = ruby_system) 14610917Sbrandon.potter@amd.com 1476906SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1488477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 1499841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1508477Snilay@cs.wisc.edu ruby_system = ruby_system) 1516906SBrad.Beckmann@amd.com 1529468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1539468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1546906SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1558257SBrad.Beckmann@amd.com 15610311Snilay@cs.wisc.edu # Connect the directory controllers and the network 15710591Snilay@cs.wisc.edu dma_cntrl.requestToDir = ruby_system.network.slave 15810591Snilay@cs.wisc.edu dma_cntrl.responseFromDir = ruby_system.network.master 15910311Snilay@cs.wisc.edu 16010519Snilay@cs.wisc.edu all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 16110311Snilay@cs.wisc.edu 16210519Snilay@cs.wisc.edu # Create the io controller and the sequencer 16310519Snilay@cs.wisc.edu if full_system: 16410519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 16510519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 16610519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 16710519Snilay@cs.wisc.edu dma_sequencer = io_seq, 16810519Snilay@cs.wisc.edu ruby_system = ruby_system) 16910519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 17010519Snilay@cs.wisc.edu 17110519Snilay@cs.wisc.edu # Connect the dma controller to the network 17210519Snilay@cs.wisc.edu io_controller.responseFromDir = ruby_system.network.master 17310519Snilay@cs.wisc.edu io_controller.requestToDir = ruby_system.network.slave 17410519Snilay@cs.wisc.edu 17510519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 17610519Snilay@cs.wisc.edu 1779100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 1789100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 179