MESI_Two_Level.py revision 9100
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 3 41 42# 43# Note: the L2 Cache latency is not currently used 44# 45class L2Cache(RubyCache): 46 latency = 15 47 48def define_options(parser): 49 return 50 51def create_system(options, system, piobus, dma_ports, ruby_system): 52 53 if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': 54 panic("This script requires the MESI_CMP_directory protocol to be built.") 55 56 cpu_sequencers = [] 57 58 # 59 # The ruby network creation expects the list of nodes in the system to be 60 # consistent with the NetDest list. Therefore the l1 controller nodes must be 61 # listed before the directory nodes and directory nodes before dma nodes, etc. 62 # 63 l1_cntrl_nodes = [] 64 l2_cntrl_nodes = [] 65 dir_cntrl_nodes = [] 66 dma_cntrl_nodes = [] 67 68 # 69 # Must create the individual controllers before the network to ensure the 70 # controller constructors are called before the network constructor 71 # 72 l2_bits = int(math.log(options.num_l2caches, 2)) 73 block_size_bits = int(math.log(options.cacheline_size, 2)) 74 75 cntrl_count = 0 76 77 for i in xrange(options.num_cpus): 78 # 79 # First create the Ruby objects associated with this cpu 80 # 81 l1i_cache = L1Cache(size = options.l1i_size, 82 assoc = options.l1i_assoc, 83 start_index_bit = block_size_bits) 84 l1d_cache = L1Cache(size = options.l1d_size, 85 assoc = options.l1d_assoc, 86 start_index_bit = block_size_bits) 87 88 l1_cntrl = L1Cache_Controller(version = i, 89 cntrl_id = cntrl_count, 90 L1IcacheMemory = l1i_cache, 91 L1DcacheMemory = l1d_cache, 92 l2_select_num_bits = l2_bits, 93 send_evictions = ( 94 options.cpu_type == "detailed"), 95 ruby_system = ruby_system) 96 97 cpu_seq = RubySequencer(version = i, 98 icache = l1i_cache, 99 dcache = l1d_cache, 100 ruby_system = ruby_system) 101 102 l1_cntrl.sequencer = cpu_seq 103 104 if piobus != None: 105 cpu_seq.pio_port = piobus.slave 106 107 exec("system.l1_cntrl%d = l1_cntrl" % i) 108 109 # 110 # Add controllers and sequencers to the appropriate lists 111 # 112 cpu_sequencers.append(cpu_seq) 113 l1_cntrl_nodes.append(l1_cntrl) 114 115 cntrl_count += 1 116 117 l2_index_start = block_size_bits + l2_bits 118 119 for i in xrange(options.num_l2caches): 120 # 121 # First create the Ruby objects associated with this cpu 122 # 123 l2_cache = L2Cache(size = options.l2_size, 124 assoc = options.l2_assoc, 125 start_index_bit = l2_index_start) 126 127 l2_cntrl = L2Cache_Controller(version = i, 128 cntrl_id = cntrl_count, 129 L2cacheMemory = l2_cache, 130 ruby_system = ruby_system) 131 132 exec("system.l2_cntrl%d = l2_cntrl" % i) 133 l2_cntrl_nodes.append(l2_cntrl) 134 135 cntrl_count += 1 136 137 phys_mem_size = 0 138 for mem in system.memories.unproxy(system): 139 phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1 140 mem_module_size = phys_mem_size / options.num_dirs 141 142 for i in xrange(options.num_dirs): 143 # 144 # Create the Ruby objects associated with the directory controller 145 # 146 147 mem_cntrl = RubyMemoryControl(version = i) 148 149 dir_size = MemorySize('0B') 150 dir_size.value = mem_module_size 151 152 dir_cntrl = Directory_Controller(version = i, 153 cntrl_id = cntrl_count, 154 directory = \ 155 RubyDirectoryMemory(version = i, 156 size = dir_size, 157 use_map = 158 options.use_map), 159 memBuffer = mem_cntrl, 160 ruby_system = ruby_system) 161 162 exec("system.dir_cntrl%d = dir_cntrl" % i) 163 dir_cntrl_nodes.append(dir_cntrl) 164 165 cntrl_count += 1 166 167 for i, dma_port in enumerate(dma_ports): 168 # 169 # Create the Ruby objects associated with the dma controller 170 # 171 dma_seq = DMASequencer(version = i, 172 ruby_system = ruby_system) 173 174 dma_cntrl = DMA_Controller(version = i, 175 cntrl_id = cntrl_count, 176 dma_sequencer = dma_seq, 177 ruby_system = ruby_system) 178 179 exec("system.dma_cntrl%d = dma_cntrl" % i) 180 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 181 dma_cntrl_nodes.append(dma_cntrl) 182 cntrl_count += 1 183 184 all_cntrls = l1_cntrl_nodes + \ 185 l2_cntrl_nodes + \ 186 dir_cntrl_nodes + \ 187 dma_cntrl_nodes 188 189 topology = create_topology(all_cntrls, options) 190 191 return (cpu_sequencers, dir_cntrl_nodes, topology) 192