MESI_Two_Level.py revision 12065:e3e51756dfef
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology, create_directories 35from Ruby import send_evicts 36 37# 38# Declare caches used by the protocol 39# 40class L1Cache(RubyCache): pass 41class L2Cache(RubyCache): pass 42 43def define_options(parser): 44 return 45 46def create_system(options, full_system, system, dma_ports, ruby_system): 47 48 if buildEnv['PROTOCOL'] != 'MESI_Two_Level': 49 fatal("This script requires the MESI_Two_Level protocol to be built.") 50 51 cpu_sequencers = [] 52 53 # 54 # The ruby network creation expects the list of nodes in the system to be 55 # consistent with the NetDest list. Therefore the l1 controller nodes must be 56 # listed before the directory nodes and directory nodes before dma nodes, etc. 57 # 58 l1_cntrl_nodes = [] 59 l2_cntrl_nodes = [] 60 dma_cntrl_nodes = [] 61 62 # 63 # Must create the individual controllers before the network to ensure the 64 # controller constructors are called before the network constructor 65 # 66 l2_bits = int(math.log(options.num_l2caches, 2)) 67 block_size_bits = int(math.log(options.cacheline_size, 2)) 68 69 for i in xrange(options.num_cpus): 70 # 71 # First create the Ruby objects associated with this cpu 72 # 73 l1i_cache = L1Cache(size = options.l1i_size, 74 assoc = options.l1i_assoc, 75 start_index_bit = block_size_bits, 76 is_icache = True) 77 l1d_cache = L1Cache(size = options.l1d_size, 78 assoc = options.l1d_assoc, 79 start_index_bit = block_size_bits, 80 is_icache = False) 81 82 prefetcher = RubyPrefetcher.Prefetcher() 83 84 # the ruby random tester reuses num_cpus to specify the 85 # number of cpu ports connected to the tester object, which 86 # is stored in system.cpu. because there is only ever one 87 # tester object, num_cpus is not necessarily equal to the 88 # size of system.cpu; therefore if len(system.cpu) == 1 89 # we use system.cpu[0] to set the clk_domain, thereby ensuring 90 # we don't index off the end of the cpu list. 91 if len(system.cpu) == 1: 92 clk_domain = system.cpu[0].clk_domain 93 else: 94 clk_domain = system.cpu[i].clk_domain 95 96 l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, 97 L1Dcache = l1d_cache, 98 l2_select_num_bits = l2_bits, 99 send_evictions = send_evicts(options), 100 prefetcher = prefetcher, 101 ruby_system = ruby_system, 102 clk_domain = clk_domain, 103 transitions_per_cycle = options.ports, 104 enable_prefetch = False) 105 106 cpu_seq = RubySequencer(version = i, icache = l1i_cache, 107 dcache = l1d_cache, clk_domain = clk_domain, 108 ruby_system = ruby_system) 109 110 111 l1_cntrl.sequencer = cpu_seq 112 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 113 114 # Add controllers and sequencers to the appropriate lists 115 cpu_sequencers.append(cpu_seq) 116 l1_cntrl_nodes.append(l1_cntrl) 117 118 # Connect the L1 controllers and the network 119 l1_cntrl.mandatoryQueue = MessageBuffer() 120 l1_cntrl.requestFromL1Cache = MessageBuffer() 121 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 122 l1_cntrl.responseFromL1Cache = MessageBuffer() 123 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 124 l1_cntrl.unblockFromL1Cache = MessageBuffer() 125 l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave 126 127 l1_cntrl.optionalQueue = MessageBuffer() 128 129 l1_cntrl.requestToL1Cache = MessageBuffer() 130 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 131 l1_cntrl.responseToL1Cache = MessageBuffer() 132 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 133 134 135 l2_index_start = block_size_bits + l2_bits 136 137 for i in xrange(options.num_l2caches): 138 # 139 # First create the Ruby objects associated with this cpu 140 # 141 l2_cache = L2Cache(size = options.l2_size, 142 assoc = options.l2_assoc, 143 start_index_bit = l2_index_start) 144 145 l2_cntrl = L2Cache_Controller(version = i, 146 L2cache = l2_cache, 147 transitions_per_cycle = options.ports, 148 ruby_system = ruby_system) 149 150 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 151 l2_cntrl_nodes.append(l2_cntrl) 152 153 # Connect the L2 controllers and the network 154 l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 155 l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 156 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 157 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 158 l2_cntrl.responseFromL2Cache = MessageBuffer() 159 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 160 161 l2_cntrl.unblockToL2Cache = MessageBuffer() 162 l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master 163 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 164 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 165 l2_cntrl.responseToL2Cache = MessageBuffer() 166 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 167 168 169 # Run each of the ruby memory controllers at a ratio of the frequency of 170 # the ruby system 171 # clk_divider value is a fix to pass regression. 172 ruby_system.memctrl_clk_domain = DerivedClockDomain( 173 clk_domain = ruby_system.clk_domain, 174 clk_divider = 3) 175 176 dir_cntrl_nodes = create_directories(options, system.mem_ranges, 177 ruby_system) 178 for dir_cntrl in dir_cntrl_nodes: 179 # Connect the directory controllers and the network 180 dir_cntrl.requestToDir = MessageBuffer() 181 dir_cntrl.requestToDir.slave = ruby_system.network.master 182 dir_cntrl.responseToDir = MessageBuffer() 183 dir_cntrl.responseToDir.slave = ruby_system.network.master 184 dir_cntrl.responseFromDir = MessageBuffer() 185 dir_cntrl.responseFromDir.master = ruby_system.network.slave 186 dir_cntrl.responseFromMemory = MessageBuffer() 187 188 189 for i, dma_port in enumerate(dma_ports): 190 # Create the Ruby objects associated with the dma controller 191 dma_seq = DMASequencer(version = i, ruby_system = ruby_system, 192 slave = dma_port) 193 194 dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, 195 transitions_per_cycle = options.ports, 196 ruby_system = ruby_system) 197 198 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 199 dma_cntrl_nodes.append(dma_cntrl) 200 201 # Connect the dma controller to the network 202 dma_cntrl.mandatoryQueue = MessageBuffer() 203 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 204 dma_cntrl.responseFromDir.slave = ruby_system.network.master 205 dma_cntrl.requestToDir = MessageBuffer() 206 dma_cntrl.requestToDir.master = ruby_system.network.slave 207 208 all_cntrls = l1_cntrl_nodes + \ 209 l2_cntrl_nodes + \ 210 dir_cntrl_nodes + \ 211 dma_cntrl_nodes 212 213 # Create the io controller and the sequencer 214 if full_system: 215 io_seq = DMASequencer(version = len(dma_ports), 216 ruby_system = ruby_system) 217 ruby_system._io_port = io_seq 218 io_controller = DMA_Controller(version = len(dma_ports), 219 dma_sequencer = io_seq, 220 ruby_system = ruby_system) 221 ruby_system.io_controller = io_controller 222 223 # Connect the dma controller to the network 224 io_controller.mandatoryQueue = MessageBuffer() 225 io_controller.responseFromDir = MessageBuffer(ordered = True) 226 io_controller.responseFromDir.slave = ruby_system.network.master 227 io_controller.requestToDir = MessageBuffer() 228 io_controller.requestToDir.master = ruby_system.network.slave 229 230 all_cntrls = all_cntrls + [io_controller] 231 232 ruby_system.network.number_of_virtual_networks = 3 233 topology = create_topology(all_cntrls, options) 234 return (cpu_sequencers, dir_cntrl_nodes, topology) 235