MESI_Two_Level.py revision 11019:fc1e41e88fd3
12207SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22207SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 32207SN/A# All rights reserved. 42207SN/A# 52207SN/A# Redistribution and use in source and binary forms, with or without 62207SN/A# modification, are permitted provided that the following conditions are 72207SN/A# met: redistributions of source code must retain the above copyright 82207SN/A# notice, this list of conditions and the following disclaimer; 92207SN/A# redistributions in binary form must reproduce the above copyright 102207SN/A# notice, this list of conditions and the following disclaimer in the 112207SN/A# documentation and/or other materials provided with the distribution; 122207SN/A# neither the name of the copyright holders nor the names of its 132207SN/A# contributors may be used to endorse or promote products derived from 142207SN/A# this software without specific prior written permission. 152207SN/A# 162207SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 292665Ssaidi@eecs.umich.edu 302207SN/Aimport math 312207SN/Aimport m5 325569Snate@binkert.orgfrom m5.objects import * 335569Snate@binkert.orgfrom m5.defines import buildEnv 342207SN/Afrom Ruby import create_topology 352474SN/Afrom Ruby import send_evicts 362207SN/A 372474SN/A# 382207SN/A# Declare caches used by the protocol 397532Ssteve.reinhardt@amd.com# 407532Ssteve.reinhardt@amd.comclass L1Cache(RubyCache): pass 417532Ssteve.reinhardt@amd.comclass L2Cache(RubyCache): pass 422474SN/A 435569Snate@binkert.orgdef define_options(parser): 442207SN/A return 4511168Sandreas.hansson@arm.com 467532Ssteve.reinhardt@amd.comdef create_system(options, full_system, system, dma_ports, ruby_system): 475759Shsul@eecs.umich.edu 485759Shsul@eecs.umich.edu if buildEnv['PROTOCOL'] != 'MESI_Two_Level': 495958Sgblack@eecs.umich.edu fatal("This script requires the MESI_Two_Level protocol to be built.") 505958Sgblack@eecs.umich.edu 516701Sgblack@eecs.umich.edu cpu_sequencers = [] 529552Sandreas.hansson@arm.com 539552Sandreas.hansson@arm.com # 545958Sgblack@eecs.umich.edu # The ruby network creation expects the list of nodes in the system to be 555958Sgblack@eecs.umich.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 562474SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 572474SN/A # 5810299Salexandru.dutu@amd.com l1_cntrl_nodes = [] 5910299Salexandru.dutu@amd.com l2_cntrl_nodes = [] 6010299Salexandru.dutu@amd.com dir_cntrl_nodes = [] 615569Snate@binkert.org dma_cntrl_nodes = [] 62 63 # 64 # Must create the individual controllers before the network to ensure the 65 # controller constructors are called before the network constructor 66 # 67 l2_bits = int(math.log(options.num_l2caches, 2)) 68 block_size_bits = int(math.log(options.cacheline_size, 2)) 69 70 for i in xrange(options.num_cpus): 71 # 72 # First create the Ruby objects associated with this cpu 73 # 74 l1i_cache = L1Cache(size = options.l1i_size, 75 assoc = options.l1i_assoc, 76 start_index_bit = block_size_bits, 77 is_icache = True) 78 l1d_cache = L1Cache(size = options.l1d_size, 79 assoc = options.l1d_assoc, 80 start_index_bit = block_size_bits, 81 is_icache = False) 82 83 prefetcher = RubyPrefetcher.Prefetcher() 84 85 l1_cntrl = L1Cache_Controller(version = i, 86 L1Icache = l1i_cache, 87 L1Dcache = l1d_cache, 88 l2_select_num_bits = l2_bits, 89 send_evictions = send_evicts(options), 90 prefetcher = prefetcher, 91 ruby_system = ruby_system, 92 clk_domain=system.cpu[i].clk_domain, 93 transitions_per_cycle=options.ports, 94 enable_prefetch = False) 95 96 cpu_seq = RubySequencer(version = i, 97 icache = l1i_cache, 98 dcache = l1d_cache, 99 clk_domain=system.cpu[i].clk_domain, 100 ruby_system = ruby_system) 101 102 l1_cntrl.sequencer = cpu_seq 103 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 104 105 # Add controllers and sequencers to the appropriate lists 106 cpu_sequencers.append(cpu_seq) 107 l1_cntrl_nodes.append(l1_cntrl) 108 109 # Connect the L1 controllers and the network 110 l1_cntrl.requestFromL1Cache = ruby_system.network.slave 111 l1_cntrl.responseFromL1Cache = ruby_system.network.slave 112 l1_cntrl.unblockFromL1Cache = ruby_system.network.slave 113 114 l1_cntrl.requestToL1Cache = ruby_system.network.master 115 l1_cntrl.responseToL1Cache = ruby_system.network.master 116 117 118 l2_index_start = block_size_bits + l2_bits 119 120 for i in xrange(options.num_l2caches): 121 # 122 # First create the Ruby objects associated with this cpu 123 # 124 l2_cache = L2Cache(size = options.l2_size, 125 assoc = options.l2_assoc, 126 start_index_bit = l2_index_start) 127 128 l2_cntrl = L2Cache_Controller(version = i, 129 L2cache = l2_cache, 130 transitions_per_cycle=options.ports, 131 ruby_system = ruby_system) 132 133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 134 l2_cntrl_nodes.append(l2_cntrl) 135 136 # Connect the L2 controllers and the network 137 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 138 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 139 l2_cntrl.responseFromL2Cache = ruby_system.network.slave 140 141 l2_cntrl.unblockToL2Cache = ruby_system.network.master 142 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 143 l2_cntrl.responseToL2Cache = ruby_system.network.master 144 145 146 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 147 assert(phys_mem_size % options.num_dirs == 0) 148 mem_module_size = phys_mem_size / options.num_dirs 149 150 151 # Run each of the ruby memory controllers at a ratio of the frequency of 152 # the ruby system 153 # clk_divider value is a fix to pass regression. 154 ruby_system.memctrl_clk_domain = DerivedClockDomain( 155 clk_domain=ruby_system.clk_domain, 156 clk_divider=3) 157 158 for i in xrange(options.num_dirs): 159 dir_size = MemorySize('0B') 160 dir_size.value = mem_module_size 161 162 dir_cntrl = Directory_Controller(version = i, 163 directory = RubyDirectoryMemory( 164 version = i, size = dir_size), 165 transitions_per_cycle = options.ports, 166 ruby_system = ruby_system) 167 168 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 169 dir_cntrl_nodes.append(dir_cntrl) 170 171 # Connect the directory controllers and the network 172 dir_cntrl.requestToDir = ruby_system.network.master 173 dir_cntrl.responseToDir = ruby_system.network.master 174 dir_cntrl.responseFromDir = ruby_system.network.slave 175 176 177 for i, dma_port in enumerate(dma_ports): 178 # Create the Ruby objects associated with the dma controller 179 dma_seq = DMASequencer(version = i, 180 ruby_system = ruby_system, 181 slave = dma_port) 182 183 dma_cntrl = DMA_Controller(version = i, 184 dma_sequencer = dma_seq, 185 transitions_per_cycle = options.ports, 186 ruby_system = ruby_system) 187 188 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 189 dma_cntrl_nodes.append(dma_cntrl) 190 191 # Connect the dma controller to the network 192 dma_cntrl.responseFromDir = ruby_system.network.master 193 dma_cntrl.requestToDir = ruby_system.network.slave 194 195 all_cntrls = l1_cntrl_nodes + \ 196 l2_cntrl_nodes + \ 197 dir_cntrl_nodes + \ 198 dma_cntrl_nodes 199 200 # Create the io controller and the sequencer 201 if full_system: 202 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 203 ruby_system._io_port = io_seq 204 io_controller = DMA_Controller(version = len(dma_ports), 205 dma_sequencer = io_seq, 206 ruby_system = ruby_system) 207 ruby_system.io_controller = io_controller 208 209 # Connect the dma controller to the network 210 io_controller.responseFromDir = ruby_system.network.master 211 io_controller.requestToDir = ruby_system.network.slave 212 213 all_cntrls = all_cntrls + [io_controller] 214 215 topology = create_topology(all_cntrls, options) 216 return (cpu_sequencers, dir_cntrl_nodes, topology) 217