MESI_Two_Level.py revision 9841
18889Sgeoffrey.blake@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 28889Sgeoffrey.blake@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 38889Sgeoffrey.blake@arm.com# All rights reserved. 48889Sgeoffrey.blake@arm.com# 58889Sgeoffrey.blake@arm.com# Redistribution and use in source and binary forms, with or without 68889Sgeoffrey.blake@arm.com# modification, are permitted provided that the following conditions are 78889Sgeoffrey.blake@arm.com# met: redistributions of source code must retain the above copyright 88889Sgeoffrey.blake@arm.com# notice, this list of conditions and the following disclaimer; 98889Sgeoffrey.blake@arm.com# redistributions in binary form must reproduce the above copyright 108889Sgeoffrey.blake@arm.com# notice, this list of conditions and the following disclaimer in the 118889Sgeoffrey.blake@arm.com# documentation and/or other materials provided with the distribution; 128889Sgeoffrey.blake@arm.com# neither the name of the copyright holders nor the names of its 138889Sgeoffrey.blake@arm.com# contributors may be used to endorse or promote products derived from 148889Sgeoffrey.blake@arm.com# this software without specific prior written permission. 158889Sgeoffrey.blake@arm.com# 168889Sgeoffrey.blake@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178889Sgeoffrey.blake@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188889Sgeoffrey.blake@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198889Sgeoffrey.blake@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208889Sgeoffrey.blake@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218889Sgeoffrey.blake@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228889Sgeoffrey.blake@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238889Sgeoffrey.blake@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248889Sgeoffrey.blake@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258889Sgeoffrey.blake@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268889Sgeoffrey.blake@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278889Sgeoffrey.blake@arm.com# 288889Sgeoffrey.blake@arm.com# Authors: Brad Beckmann 298889Sgeoffrey.blake@arm.com 308889Sgeoffrey.blake@arm.comimport math 318889Sgeoffrey.blake@arm.comimport m5 328889Sgeoffrey.blake@arm.comfrom m5.objects import * 338889Sgeoffrey.blake@arm.comfrom m5.defines import buildEnv 348889Sgeoffrey.blake@arm.comfrom Ruby import create_topology 358889Sgeoffrey.blake@arm.com 368889Sgeoffrey.blake@arm.com# 378889Sgeoffrey.blake@arm.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 388889Sgeoffrey.blake@arm.com# 398889Sgeoffrey.blake@arm.comclass L1Cache(RubyCache): 408889Sgeoffrey.blake@arm.com latency = 3 418889Sgeoffrey.blake@arm.com 428889Sgeoffrey.blake@arm.com# 438889Sgeoffrey.blake@arm.com# Note: the L2 Cache latency is not currently used 448889Sgeoffrey.blake@arm.com# 458889Sgeoffrey.blake@arm.comclass L2Cache(RubyCache): 468889Sgeoffrey.blake@arm.com latency = 15 478889Sgeoffrey.blake@arm.com 488889Sgeoffrey.blake@arm.comdef define_options(parser): 498889Sgeoffrey.blake@arm.com return 508889Sgeoffrey.blake@arm.com 518889Sgeoffrey.blake@arm.comdef create_system(options, system, piobus, dma_ports, ruby_system): 528889Sgeoffrey.blake@arm.com 538889Sgeoffrey.blake@arm.com if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': 548889Sgeoffrey.blake@arm.com panic("This script requires the MESI_CMP_directory protocol to be built.") 558889Sgeoffrey.blake@arm.com 568889Sgeoffrey.blake@arm.com cpu_sequencers = [] 578889Sgeoffrey.blake@arm.com 588889Sgeoffrey.blake@arm.com # 598889Sgeoffrey.blake@arm.com # The ruby network creation expects the list of nodes in the system to be 608889Sgeoffrey.blake@arm.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 618889Sgeoffrey.blake@arm.com # listed before the directory nodes and directory nodes before dma nodes, etc. 628889Sgeoffrey.blake@arm.com # 638889Sgeoffrey.blake@arm.com l1_cntrl_nodes = [] 648889Sgeoffrey.blake@arm.com l2_cntrl_nodes = [] 658889Sgeoffrey.blake@arm.com dir_cntrl_nodes = [] 668889Sgeoffrey.blake@arm.com dma_cntrl_nodes = [] 678889Sgeoffrey.blake@arm.com 688889Sgeoffrey.blake@arm.com # 69 # Must create the individual controllers before the network to ensure the 70 # controller constructors are called before the network constructor 71 # 72 l2_bits = int(math.log(options.num_l2caches, 2)) 73 block_size_bits = int(math.log(options.cacheline_size, 2)) 74 75 cntrl_count = 0 76 77 for i in xrange(options.num_cpus): 78 # 79 # First create the Ruby objects associated with this cpu 80 # 81 l1i_cache = L1Cache(size = options.l1i_size, 82 assoc = options.l1i_assoc, 83 start_index_bit = block_size_bits, 84 is_icache = True) 85 l1d_cache = L1Cache(size = options.l1d_size, 86 assoc = options.l1d_assoc, 87 start_index_bit = block_size_bits, 88 is_icache = False) 89 90 prefetcher = RubyPrefetcher.Prefetcher() 91 92 l1_cntrl = L1Cache_Controller(version = i, 93 cntrl_id = cntrl_count, 94 L1Icache = l1i_cache, 95 L1Dcache = l1d_cache, 96 l2_select_num_bits = l2_bits, 97 send_evictions = ( 98 options.cpu_type == "detailed"), 99 prefetcher = prefetcher, 100 ruby_system = ruby_system, 101 transitions_per_cycle=options.ports, 102 enable_prefetch = False) 103 104 cpu_seq = RubySequencer(version = i, 105 icache = l1i_cache, 106 dcache = l1d_cache, 107 ruby_system = ruby_system) 108 109 l1_cntrl.sequencer = cpu_seq 110 111 if piobus != None: 112 cpu_seq.pio_port = piobus.slave 113 114 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 115 116 # 117 # Add controllers and sequencers to the appropriate lists 118 # 119 cpu_sequencers.append(cpu_seq) 120 l1_cntrl_nodes.append(l1_cntrl) 121 122 cntrl_count += 1 123 124 l2_index_start = block_size_bits + l2_bits 125 126 for i in xrange(options.num_l2caches): 127 # 128 # First create the Ruby objects associated with this cpu 129 # 130 l2_cache = L2Cache(size = options.l2_size, 131 assoc = options.l2_assoc, 132 start_index_bit = l2_index_start) 133 134 l2_cntrl = L2Cache_Controller(version = i, 135 cntrl_id = cntrl_count, 136 L2cache = l2_cache, 137 transitions_per_cycle=options.ports, 138 ruby_system = ruby_system) 139 140 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 141 l2_cntrl_nodes.append(l2_cntrl) 142 143 cntrl_count += 1 144 145 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 146 assert(phys_mem_size % options.num_dirs == 0) 147 mem_module_size = phys_mem_size / options.num_dirs 148 149 # Run each of the ruby memory controllers at a ratio of the frequency of 150 # the ruby system 151 # clk_divider value is a fix to pass regression. 152 ruby_system.memctrl_clk_domain = DerivedClockDomain( 153 clk_domain=ruby_system.clk_domain, 154 clk_divider=3) 155 156 for i in xrange(options.num_dirs): 157 # 158 # Create the Ruby objects associated with the directory controller 159 # 160 161 mem_cntrl = RubyMemoryControl( 162 clk_domain = ruby_system.memctrl_clk_domain, 163 version = i, 164 ruby_system = ruby_system) 165 166 dir_size = MemorySize('0B') 167 dir_size.value = mem_module_size 168 169 dir_cntrl = Directory_Controller(version = i, 170 cntrl_id = cntrl_count, 171 directory = \ 172 RubyDirectoryMemory(version = i, 173 size = dir_size, 174 use_map = 175 options.use_map), 176 memBuffer = mem_cntrl, 177 transitions_per_cycle = options.ports, 178 ruby_system = ruby_system) 179 180 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 181 dir_cntrl_nodes.append(dir_cntrl) 182 183 cntrl_count += 1 184 185 for i, dma_port in enumerate(dma_ports): 186 # 187 # Create the Ruby objects associated with the dma controller 188 # 189 dma_seq = DMASequencer(version = i, 190 ruby_system = ruby_system) 191 192 dma_cntrl = DMA_Controller(version = i, 193 cntrl_id = cntrl_count, 194 dma_sequencer = dma_seq, 195 transitions_per_cycle = options.ports, 196 ruby_system = ruby_system) 197 198 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 199 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 200 dma_cntrl_nodes.append(dma_cntrl) 201 cntrl_count += 1 202 203 all_cntrls = l1_cntrl_nodes + \ 204 l2_cntrl_nodes + \ 205 dir_cntrl_nodes + \ 206 dma_cntrl_nodes 207 208 topology = create_topology(all_cntrls, options) 209 210 return (cpu_sequencers, dir_cntrl_nodes, topology) 211