MESI_Two_Level.py revision 9696
12810Srdreslin@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 22810Srdreslin@umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 32810Srdreslin@umich.edu# All rights reserved. 42810Srdreslin@umich.edu# 52810Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu# this software without specific prior written permission. 152810Srdreslin@umich.edu# 162810Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu# 282810Srdreslin@umich.edu# Authors: Brad Beckmann 292810Srdreslin@umich.edu 302810Srdreslin@umich.eduimport math 312810Srdreslin@umich.eduimport m5 322810Srdreslin@umich.edufrom m5.objects import * 332810Srdreslin@umich.edufrom m5.defines import buildEnv 342810Srdreslin@umich.edufrom Ruby import create_topology 352810Srdreslin@umich.edu 362810Srdreslin@umich.edu# 372810Srdreslin@umich.edu# Note: the L1 Cache latency is only used by the sequencer on fast path hits 382810Srdreslin@umich.edu# 392810Srdreslin@umich.educlass L1Cache(RubyCache): 402810Srdreslin@umich.edu latency = 3 412810Srdreslin@umich.edu 422810Srdreslin@umich.edu# 432810Srdreslin@umich.edu# Note: the L2 Cache latency is not currently used 442810Srdreslin@umich.edu# 452810Srdreslin@umich.educlass L2Cache(RubyCache): 462810Srdreslin@umich.edu latency = 15 472813Srdreslin@umich.edu 482813Srdreslin@umich.edudef define_options(parser): 492813Srdreslin@umich.edu return 502810Srdreslin@umich.edu 512810Srdreslin@umich.edudef create_system(options, system, piobus, dma_ports, ruby_system): 522810Srdreslin@umich.edu 532810Srdreslin@umich.edu if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': 542810Srdreslin@umich.edu panic("This script requires the MESI_CMP_directory protocol to be built.") 552810Srdreslin@umich.edu 562810Srdreslin@umich.edu cpu_sequencers = [] 572810Srdreslin@umich.edu 582810Srdreslin@umich.edu # 592810Srdreslin@umich.edu # The ruby network creation expects the list of nodes in the system to be 602810Srdreslin@umich.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 612810Srdreslin@umich.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 622810Srdreslin@umich.edu # 632810Srdreslin@umich.edu l1_cntrl_nodes = [] 642810Srdreslin@umich.edu l2_cntrl_nodes = [] 652810Srdreslin@umich.edu dir_cntrl_nodes = [] 662810Srdreslin@umich.edu dma_cntrl_nodes = [] 672810Srdreslin@umich.edu 682810Srdreslin@umich.edu # 692810Srdreslin@umich.edu # Must create the individual controllers before the network to ensure the 702810Srdreslin@umich.edu # controller constructors are called before the network constructor 712810Srdreslin@umich.edu # 722810Srdreslin@umich.edu l2_bits = int(math.log(options.num_l2caches, 2)) 732810Srdreslin@umich.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 742810Srdreslin@umich.edu 752810Srdreslin@umich.edu cntrl_count = 0 762810Srdreslin@umich.edu 772810Srdreslin@umich.edu for i in xrange(options.num_cpus): 782810Srdreslin@umich.edu # 792810Srdreslin@umich.edu # First create the Ruby objects associated with this cpu 802810Srdreslin@umich.edu # 812810Srdreslin@umich.edu l1i_cache = L1Cache(size = options.l1i_size, 822810Srdreslin@umich.edu assoc = options.l1i_assoc, 832810Srdreslin@umich.edu start_index_bit = block_size_bits, 842810Srdreslin@umich.edu is_icache = True) 852810Srdreslin@umich.edu l1d_cache = L1Cache(size = options.l1d_size, 862810Srdreslin@umich.edu assoc = options.l1d_assoc, 872810Srdreslin@umich.edu start_index_bit = block_size_bits, 882810Srdreslin@umich.edu is_icache = False) 892810Srdreslin@umich.edu 902810Srdreslin@umich.edu prefetcher = RubyPrefetcher.Prefetcher() 912810Srdreslin@umich.edu 922810Srdreslin@umich.edu l1_cntrl = L1Cache_Controller(version = i, 932810Srdreslin@umich.edu cntrl_id = cntrl_count, 942810Srdreslin@umich.edu L1Icache = l1i_cache, 952810Srdreslin@umich.edu L1Dcache = l1d_cache, 962813Srdreslin@umich.edu l2_select_num_bits = l2_bits, 972813Srdreslin@umich.edu send_evictions = ( 982813Srdreslin@umich.edu options.cpu_type == "detailed"), 992813Srdreslin@umich.edu prefetcher = prefetcher, 1002813Srdreslin@umich.edu ruby_system = ruby_system, 1012810Srdreslin@umich.edu enable_prefetch = False) 1022810Srdreslin@umich.edu 1032810Srdreslin@umich.edu cpu_seq = RubySequencer(version = i, 1042810Srdreslin@umich.edu icache = l1i_cache, 1052810Srdreslin@umich.edu dcache = l1d_cache, 1062810Srdreslin@umich.edu ruby_system = ruby_system) 1072810Srdreslin@umich.edu 1082810Srdreslin@umich.edu l1_cntrl.sequencer = cpu_seq 1092810Srdreslin@umich.edu 1102810Srdreslin@umich.edu if piobus != None: 1112810Srdreslin@umich.edu cpu_seq.pio_port = piobus.slave 1122810Srdreslin@umich.edu 1132810Srdreslin@umich.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1142810Srdreslin@umich.edu 1152810Srdreslin@umich.edu # 1162810Srdreslin@umich.edu # Add controllers and sequencers to the appropriate lists 1172810Srdreslin@umich.edu # 1182810Srdreslin@umich.edu cpu_sequencers.append(cpu_seq) 1192810Srdreslin@umich.edu l1_cntrl_nodes.append(l1_cntrl) 1202810Srdreslin@umich.edu 1212810Srdreslin@umich.edu cntrl_count += 1 1222810Srdreslin@umich.edu 1232810Srdreslin@umich.edu l2_index_start = block_size_bits + l2_bits 1242810Srdreslin@umich.edu 1252810Srdreslin@umich.edu for i in xrange(options.num_l2caches): 1262810Srdreslin@umich.edu # 1272810Srdreslin@umich.edu # First create the Ruby objects associated with this cpu 1282810Srdreslin@umich.edu # 1292810Srdreslin@umich.edu l2_cache = L2Cache(size = options.l2_size, 1302810Srdreslin@umich.edu assoc = options.l2_assoc, 1312810Srdreslin@umich.edu start_index_bit = l2_index_start) 1322813Srdreslin@umich.edu 1332810Srdreslin@umich.edu l2_cntrl = L2Cache_Controller(version = i, 1342810Srdreslin@umich.edu cntrl_id = cntrl_count, 1352813Srdreslin@umich.edu L2cache = l2_cache, 1362813Srdreslin@umich.edu ruby_system = ruby_system) 1372813Srdreslin@umich.edu 1382810Srdreslin@umich.edu exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1392813Srdreslin@umich.edu l2_cntrl_nodes.append(l2_cntrl) 1402813Srdreslin@umich.edu 1412813Srdreslin@umich.edu cntrl_count += 1 1422810Srdreslin@umich.edu 1432810Srdreslin@umich.edu phys_mem_size = sum(map(lambda mem: mem.range.size(), 1442810Srdreslin@umich.edu system.memories.unproxy(system))) 1452810Srdreslin@umich.edu mem_module_size = phys_mem_size / options.num_dirs 1462810Srdreslin@umich.edu 1472812Srdreslin@umich.edu for i in xrange(options.num_dirs): 1482810Srdreslin@umich.edu # 1492813Srdreslin@umich.edu # Create the Ruby objects associated with the directory controller 1502813Srdreslin@umich.edu # 1512813Srdreslin@umich.edu 1522813Srdreslin@umich.edu mem_cntrl = RubyMemoryControl(version = i, 1532813Srdreslin@umich.edu ruby_system = ruby_system) 1542813Srdreslin@umich.edu 1552813Srdreslin@umich.edu dir_size = MemorySize('0B') 1562813Srdreslin@umich.edu dir_size.value = mem_module_size 1572813Srdreslin@umich.edu 1582813Srdreslin@umich.edu dir_cntrl = Directory_Controller(version = i, 1592813Srdreslin@umich.edu cntrl_id = cntrl_count, 1602810Srdreslin@umich.edu directory = \ 1612810Srdreslin@umich.edu RubyDirectoryMemory(version = i, 1622810Srdreslin@umich.edu size = dir_size, 1632810Srdreslin@umich.edu use_map = 1642810Srdreslin@umich.edu options.use_map), 1652810Srdreslin@umich.edu memBuffer = mem_cntrl, 1662810Srdreslin@umich.edu ruby_system = ruby_system) 1672812Srdreslin@umich.edu 1682810Srdreslin@umich.edu exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1692810Srdreslin@umich.edu dir_cntrl_nodes.append(dir_cntrl) 1702810Srdreslin@umich.edu 1712810Srdreslin@umich.edu cntrl_count += 1 1722810Srdreslin@umich.edu 1732810Srdreslin@umich.edu for i, dma_port in enumerate(dma_ports): 1742810Srdreslin@umich.edu # 1752810Srdreslin@umich.edu # Create the Ruby objects associated with the dma controller 1762810Srdreslin@umich.edu # 1772810Srdreslin@umich.edu dma_seq = DMASequencer(version = i, 1782810Srdreslin@umich.edu ruby_system = ruby_system) 1792810Srdreslin@umich.edu 1802810Srdreslin@umich.edu dma_cntrl = DMA_Controller(version = i, 1812810Srdreslin@umich.edu cntrl_id = cntrl_count, 1822810Srdreslin@umich.edu dma_sequencer = dma_seq, 1832810Srdreslin@umich.edu ruby_system = ruby_system) 1842810Srdreslin@umich.edu 1852810Srdreslin@umich.edu exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1862810Srdreslin@umich.edu exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 1872810Srdreslin@umich.edu dma_cntrl_nodes.append(dma_cntrl) 1882810Srdreslin@umich.edu cntrl_count += 1 1892810Srdreslin@umich.edu 1902810Srdreslin@umich.edu all_cntrls = l1_cntrl_nodes + \ 1912810Srdreslin@umich.edu l2_cntrl_nodes + \ 1922810Srdreslin@umich.edu dir_cntrl_nodes + \ 1932810Srdreslin@umich.edu dma_cntrl_nodes 1942810Srdreslin@umich.edu 1952810Srdreslin@umich.edu topology = create_topology(all_cntrls, options) 1962810Srdreslin@umich.edu 1972810Srdreslin@umich.edu return (cpu_sequencers, dir_cntrl_nodes, topology) 1982810Srdreslin@umich.edu