MESI_Two_Level.py revision 8322
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34 35# 36# Note: the L1 Cache latency is only used by the sequencer on fast path hits 37# 38class L1Cache(RubyCache): 39 latency = 3 40 41# 42# Note: the L2 Cache latency is not currently used 43# 44class L2Cache(RubyCache): 45 latency = 15 46 47def define_options(parser): 48 return 49 50def create_system(options, system, piobus, dma_devices): 51 52 if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': 53 panic("This script requires the MESI_CMP_directory protocol to be built.") 54 55 cpu_sequencers = [] 56 57 # 58 # The ruby network creation expects the list of nodes in the system to be 59 # consistent with the NetDest list. Therefore the l1 controller nodes must be 60 # listed before the directory nodes and directory nodes before dma nodes, etc. 61 # 62 l1_cntrl_nodes = [] 63 l2_cntrl_nodes = [] 64 dir_cntrl_nodes = [] 65 dma_cntrl_nodes = [] 66 67 # 68 # Must create the individual controllers before the network to ensure the 69 # controller constructors are called before the network constructor 70 # 71 l2_bits = int(math.log(options.num_l2caches, 2)) 72 block_size_bits = int(math.log(options.cacheline_size, 2)) 73 74 cntrl_count = 0 75 76 for i in xrange(options.num_cpus): 77 # 78 # First create the Ruby objects associated with this cpu 79 # 80 l1i_cache = L1Cache(size = options.l1i_size, 81 assoc = options.l1i_assoc, 82 start_index_bit = block_size_bits) 83 l1d_cache = L1Cache(size = options.l1d_size, 84 assoc = options.l1d_assoc, 85 start_index_bit = block_size_bits) 86 87 l1_cntrl = L1Cache_Controller(version = i, 88 cntrl_id = cntrl_count, 89 L1IcacheMemory = l1i_cache, 90 L1DcacheMemory = l1d_cache, 91 l2_select_num_bits = l2_bits) 92 93 cpu_seq = RubySequencer(version = i, 94 icache = l1i_cache, 95 dcache = l1d_cache, 96 physMemPort = system.physmem.port, 97 physmem = system.physmem) 98 99 l1_cntrl.sequencer = cpu_seq 100 101 if piobus != None: 102 cpu_seq.pio_port = piobus.port 103 104 exec("system.l1_cntrl%d = l1_cntrl" % i) 105 106 # 107 # Add controllers and sequencers to the appropriate lists 108 # 109 cpu_sequencers.append(cpu_seq) 110 l1_cntrl_nodes.append(l1_cntrl) 111 112 cntrl_count += 1 113 114 l2_index_start = block_size_bits + l2_bits 115 116 for i in xrange(options.num_l2caches): 117 # 118 # First create the Ruby objects associated with this cpu 119 # 120 l2_cache = L2Cache(size = options.l2_size, 121 assoc = options.l2_assoc, 122 start_index_bit = l2_index_start) 123 124 l2_cntrl = L2Cache_Controller(version = i, 125 cntrl_id = cntrl_count, 126 L2cacheMemory = l2_cache) 127 128 exec("system.l2_cntrl%d = l2_cntrl" % i) 129 l2_cntrl_nodes.append(l2_cntrl) 130 131 cntrl_count += 1 132 133 phys_mem_size = long(system.physmem.range.second) - \ 134 long(system.physmem.range.first) + 1 135 mem_module_size = phys_mem_size / options.num_dirs 136 137 for i in xrange(options.num_dirs): 138 # 139 # Create the Ruby objects associated with the directory controller 140 # 141 142 mem_cntrl = RubyMemoryControl(version = i) 143 144 dir_size = MemorySize('0B') 145 dir_size.value = mem_module_size 146 147 dir_cntrl = Directory_Controller(version = i, 148 cntrl_id = cntrl_count, 149 directory = \ 150 RubyDirectoryMemory(version = i, 151 size = \ 152 dir_size), 153 memBuffer = mem_cntrl) 154 155 exec("system.dir_cntrl%d = dir_cntrl" % i) 156 dir_cntrl_nodes.append(dir_cntrl) 157 158 cntrl_count += 1 159 160 for i, dma_device in enumerate(dma_devices): 161 # 162 # Create the Ruby objects associated with the dma controller 163 # 164 dma_seq = DMASequencer(version = i, 165 physMemPort = system.physmem.port, 166 physmem = system.physmem) 167 168 dma_cntrl = DMA_Controller(version = i, 169 cntrl_id = cntrl_count, 170 dma_sequencer = dma_seq) 171 172 exec("system.dma_cntrl%d = dma_cntrl" % i) 173 if dma_device.type == 'MemTest': 174 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 175 else: 176 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 177 dma_cntrl_nodes.append(dma_cntrl) 178 179 cntrl_count += 1 180 181 all_cntrls = l1_cntrl_nodes + \ 182 l2_cntrl_nodes + \ 183 dir_cntrl_nodes + \ 184 dma_cntrl_nodes 185 186 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 187