MESI_Two_Level.py revision 8257
12623SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22623SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 32623SN/A# All rights reserved. 42623SN/A# 52623SN/A# Redistribution and use in source and binary forms, with or without 62623SN/A# modification, are permitted provided that the following conditions are 72623SN/A# met: redistributions of source code must retain the above copyright 82623SN/A# notice, this list of conditions and the following disclaimer; 92623SN/A# redistributions in binary form must reproduce the above copyright 102623SN/A# notice, this list of conditions and the following disclaimer in the 112623SN/A# documentation and/or other materials provided with the distribution; 122623SN/A# neither the name of the copyright holders nor the names of its 132623SN/A# contributors may be used to endorse or promote products derived from 142623SN/A# this software without specific prior written permission. 152623SN/A# 162623SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 292623SN/A 302623SN/Aimport math 313170Sstever@eecs.umich.eduimport m5 322623SN/Afrom m5.objects import * 334040Ssaidi@eecs.umich.edufrom m5.defines import buildEnv 342623SN/A 352623SN/A# 363348Sbinkertn@umich.edu# Note: the L1 Cache latency is only used by the sequencer on fast path hits 373348Sbinkertn@umich.edu# 382623SN/Aclass L1Cache(RubyCache): 392901Ssaidi@eecs.umich.edu latency = 3 402623SN/A 412623SN/A# 422623SN/A# Note: the L2 Cache latency is not currently used 432623SN/A# 442856Srdreslin@umich.educlass L2Cache(RubyCache): 452856Srdreslin@umich.edu latency = 15 462856Srdreslin@umich.edu 472856Srdreslin@umich.edudef define_options(parser): 482856Srdreslin@umich.edu return 492856Srdreslin@umich.edu 502856Srdreslin@umich.edudef create_system(options, system, piobus, dma_devices): 512856Srdreslin@umich.edu 522856Srdreslin@umich.edu if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': 532856Srdreslin@umich.edu panic("This script requires the MESI_CMP_directory protocol to be built.") 542623SN/A 552623SN/A cpu_sequencers = [] 562623SN/A 572623SN/A # 582623SN/A # The ruby network creation expects the list of nodes in the system to be 592623SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 602680Sktlim@umich.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 612680Sktlim@umich.edu # 622623SN/A l1_cntrl_nodes = [] 632623SN/A l2_cntrl_nodes = [] 642680Sktlim@umich.edu dir_cntrl_nodes = [] 652623SN/A dma_cntrl_nodes = [] 662623SN/A 672623SN/A # 682623SN/A # Must create the individual controllers before the network to ensure the 692623SN/A # controller constructors are called before the network constructor 703349Sbinkertn@umich.edu # 712623SN/A l2_bits = int(math.log(options.num_l2caches, 2)) 722623SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 732623SN/A 742623SN/A cntrl_count = 0 752623SN/A 762623SN/A for i in xrange(options.num_cpus): 773349Sbinkertn@umich.edu # 782623SN/A # First create the Ruby objects associated with this cpu 793184Srdreslin@umich.edu # 803184Srdreslin@umich.edu l1i_cache = L1Cache(size = options.l1i_size, 812623SN/A assoc = options.l1i_assoc, 822623SN/A start_index_bit = block_size_bits) 832623SN/A l1d_cache = L1Cache(size = options.l1d_size, 842623SN/A assoc = options.l1d_assoc, 852623SN/A start_index_bit = block_size_bits) 863647Srdreslin@umich.edu 873647Srdreslin@umich.edu cpu_seq = RubySequencer(version = i, 883647Srdreslin@umich.edu icache = l1i_cache, 893647Srdreslin@umich.edu dcache = l1d_cache, 903647Srdreslin@umich.edu physMemPort = system.physmem.port, 912631SN/A physmem = system.physmem) 923647Srdreslin@umich.edu 932631SN/A if piobus != None: 942623SN/A cpu_seq.pio_port = piobus.port 952623SN/A 962623SN/A l1_cntrl = L1Cache_Controller(version = i, 972948Ssaidi@eecs.umich.edu cntrl_id = cntrl_count, 982948Ssaidi@eecs.umich.edu sequencer = cpu_seq, 993349Sbinkertn@umich.edu L1IcacheMemory = l1i_cache, 1002948Ssaidi@eecs.umich.edu L1DcacheMemory = l1d_cache, 1012948Ssaidi@eecs.umich.edu l2_select_num_bits = l2_bits) 1022948Ssaidi@eecs.umich.edu 1032948Ssaidi@eecs.umich.edu exec("system.l1_cntrl%d = l1_cntrl" % i) 1042948Ssaidi@eecs.umich.edu 1052623SN/A # 1063170Sstever@eecs.umich.edu # Add controllers and sequencers to the appropriate lists 1073170Sstever@eecs.umich.edu # 1082623SN/A cpu_sequencers.append(cpu_seq) 1092623SN/A l1_cntrl_nodes.append(l1_cntrl) 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu cntrl_count += 1 1123647Srdreslin@umich.edu 1133647Srdreslin@umich.edu l2_index_start = block_size_bits + l2_bits 1142623SN/A 1152839Sktlim@umich.edu for i in xrange(options.num_l2caches): 1162867Sktlim@umich.edu # 1173222Sktlim@umich.edu # First create the Ruby objects associated with this cpu 1182901Ssaidi@eecs.umich.edu # 1192623SN/A l2_cache = L2Cache(size = options.l2_size, 1202623SN/A assoc = options.l2_assoc, 1212623SN/A start_index_bit = l2_index_start) 1222623SN/A 1232623SN/A l2_cntrl = L2Cache_Controller(version = i, 1242623SN/A cntrl_id = cntrl_count, 1252623SN/A L2cacheMemory = l2_cache) 1262623SN/A 1272623SN/A exec("system.l2_cntrl%d = l2_cntrl" % i) 1282623SN/A l2_cntrl_nodes.append(l2_cntrl) 1292915Sktlim@umich.edu 1302915Sktlim@umich.edu cntrl_count += 1 1312623SN/A 1322623SN/A phys_mem_size = long(system.physmem.range.second) - \ 1332623SN/A long(system.physmem.range.first) + 1 1342623SN/A mem_module_size = phys_mem_size / options.num_dirs 1352623SN/A 1362623SN/A for i in xrange(options.num_dirs): 1372915Sktlim@umich.edu # 1382915Sktlim@umich.edu # Create the Ruby objects associated with the directory controller 1392623SN/A # 1402798Sktlim@umich.edu 1412798Sktlim@umich.edu mem_cntrl = RubyMemoryControl(version = i) 1422901Ssaidi@eecs.umich.edu 1432839Sktlim@umich.edu dir_size = MemorySize('0B') 1442798Sktlim@umich.edu dir_size.value = mem_module_size 1452839Sktlim@umich.edu 1462798Sktlim@umich.edu dir_cntrl = Directory_Controller(version = i, 1472798Sktlim@umich.edu cntrl_id = cntrl_count, 1482901Ssaidi@eecs.umich.edu directory = \ 1492901Ssaidi@eecs.umich.edu RubyDirectoryMemory(version = i, 1502798Sktlim@umich.edu size = \ 1512839Sktlim@umich.edu dir_size), 1522839Sktlim@umich.edu memBuffer = mem_cntrl) 1532901Ssaidi@eecs.umich.edu 1542798Sktlim@umich.edu exec("system.dir_cntrl%d = dir_cntrl" % i) 1552623SN/A dir_cntrl_nodes.append(dir_cntrl) 1562623SN/A 1572623SN/A cntrl_count += 1 1582798Sktlim@umich.edu 1592623SN/A for i, dma_device in enumerate(dma_devices): 1602798Sktlim@umich.edu # 1613201Shsul@eecs.umich.edu # Create the Ruby objects associated with the dma controller 1623201Shsul@eecs.umich.edu # 1632867Sktlim@umich.edu dma_seq = DMASequencer(version = i, 1642867Sktlim@umich.edu physMemPort = system.physmem.port, 1652915Sktlim@umich.edu physmem = system.physmem) 1662915Sktlim@umich.edu 1672915Sktlim@umich.edu dma_cntrl = DMA_Controller(version = i, 1682867Sktlim@umich.edu cntrl_id = cntrl_count, 1692867Sktlim@umich.edu dma_sequencer = dma_seq) 1702867Sktlim@umich.edu 1712867Sktlim@umich.edu exec("system.dma_cntrl%d = dma_cntrl" % i) 1722867Sktlim@umich.edu if dma_device.type == 'MemTest': 1733661Srdreslin@umich.edu exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 1742623SN/A else: 1752798Sktlim@umich.edu exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 1762901Ssaidi@eecs.umich.edu dma_cntrl_nodes.append(dma_cntrl) 1773222Sktlim@umich.edu 1782798Sktlim@umich.edu cntrl_count += 1 1792798Sktlim@umich.edu 1802798Sktlim@umich.edu all_cntrls = l1_cntrl_nodes + \ 1812798Sktlim@umich.edu l2_cntrl_nodes + \ 1822798Sktlim@umich.edu dir_cntrl_nodes + \ 1832798Sktlim@umich.edu dma_cntrl_nodes 1842798Sktlim@umich.edu 1853222Sktlim@umich.edu return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 1862867Sktlim@umich.edu