MESI_Two_Level.py revision 8180 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39    latency = 3
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45    latency = 15
46
47def define_options(parser):
48    return
49
50def create_system(options, system, piobus, dma_devices):
51
52    if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
53        panic("This script requires the MESI_CMP_directory protocol to be built.")
54
55    cpu_sequencers = []
56
57    #
58    # The ruby network creation expects the list of nodes in the system to be
59    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
60    # listed before the directory nodes and directory nodes before dma nodes, etc.
61    #
62    l1_cntrl_nodes = []
63    l2_cntrl_nodes = []
64    dir_cntrl_nodes = []
65    dma_cntrl_nodes = []
66
67    #
68    # Must create the individual controllers before the network to ensure the
69    # controller constructors are called before the network constructor
70    #
71    l2_bits = int(math.log(options.num_l2caches, 2))
72    block_size_bits = int(math.log(options.cacheline_size, 2))
73
74    for i in xrange(options.num_cpus):
75        #
76        # First create the Ruby objects associated with this cpu
77        #
78        l1i_cache = L1Cache(size = options.l1i_size,
79                            assoc = options.l1i_assoc,
80                            start_index_bit = block_size_bits)
81        l1d_cache = L1Cache(size = options.l1d_size,
82                            assoc = options.l1d_assoc,
83                            start_index_bit = block_size_bits)
84
85        cpu_seq = RubySequencer(version = i,
86                                icache = l1i_cache,
87                                dcache = l1d_cache,
88                                physMemPort = system.physmem.port,
89                                physmem = system.physmem)
90
91        if piobus != None:
92            cpu_seq.pio_port = piobus.port
93
94        l1_cntrl = L1Cache_Controller(version = i,
95                                      sequencer = cpu_seq,
96                                      L1IcacheMemory = l1i_cache,
97                                      L1DcacheMemory = l1d_cache,
98                                      l2_select_num_bits = l2_bits)
99
100        exec("system.l1_cntrl%d = l1_cntrl" % i)
101
102        #
103        # Add controllers and sequencers to the appropriate lists
104        #
105        cpu_sequencers.append(cpu_seq)
106        l1_cntrl_nodes.append(l1_cntrl)
107
108    l2_index_start = block_size_bits + l2_bits
109
110    for i in xrange(options.num_l2caches):
111        #
112        # First create the Ruby objects associated with this cpu
113        #
114        l2_cache = L2Cache(size = options.l2_size,
115                           assoc = options.l2_assoc,
116                           start_index_bit = l2_index_start)
117
118        l2_cntrl = L2Cache_Controller(version = i,
119                                      L2cacheMemory = l2_cache)
120
121        exec("system.l2_cntrl%d = l2_cntrl" % i)
122        l2_cntrl_nodes.append(l2_cntrl)
123
124    phys_mem_size = long(system.physmem.range.second) - \
125                      long(system.physmem.range.first) + 1
126    mem_module_size = phys_mem_size / options.num_dirs
127
128    for i in xrange(options.num_dirs):
129        #
130        # Create the Ruby objects associated with the directory controller
131        #
132
133        mem_cntrl = RubyMemoryControl(version = i)
134
135        dir_size = MemorySize('0B')
136        dir_size.value = mem_module_size
137
138        dir_cntrl = Directory_Controller(version = i,
139                                         directory = \
140                                         RubyDirectoryMemory(version = i,
141                                                             size = \
142                                                               dir_size),
143                                         memBuffer = mem_cntrl)
144
145        exec("system.dir_cntrl%d = dir_cntrl" % i)
146        dir_cntrl_nodes.append(dir_cntrl)
147
148    for i, dma_device in enumerate(dma_devices):
149        #
150        # Create the Ruby objects associated with the dma controller
151        #
152        dma_seq = DMASequencer(version = i,
153                               physMemPort = system.physmem.port,
154                               physmem = system.physmem)
155
156        dma_cntrl = DMA_Controller(version = i,
157                                   dma_sequencer = dma_seq)
158
159        exec("system.dma_cntrl%d = dma_cntrl" % i)
160        if dma_device.type == 'MemTest':
161            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
162        else:
163            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
164        dma_cntrl_nodes.append(dma_cntrl)
165
166    all_cntrls = l1_cntrl_nodes + \
167                 l2_cntrl_nodes + \
168                 dir_cntrl_nodes + \
169                 dma_cntrl_nodes
170
171    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
172