MESI_Two_Level.py revision 12065
16915SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26915SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 36915SN/A# All rights reserved. 46915SN/A# 56915SN/A# Redistribution and use in source and binary forms, with or without 66915SN/A# modification, are permitted provided that the following conditions are 76915SN/A# met: redistributions of source code must retain the above copyright 86915SN/A# notice, this list of conditions and the following disclaimer; 96915SN/A# redistributions in binary form must reproduce the above copyright 106915SN/A# notice, this list of conditions and the following disclaimer in the 116915SN/A# documentation and/or other materials provided with the distribution; 126915SN/A# neither the name of the copyright holders nor the names of its 136915SN/A# contributors may be used to endorse or promote products derived from 146915SN/A# this software without specific prior written permission. 156915SN/A# 166915SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176915SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186915SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196915SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206915SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216915SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226915SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236915SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246915SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256915SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266915SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276915SN/A# 286915SN/A# Authors: Brad Beckmann 296915SN/A 306915SN/Aimport math 316915SN/Aimport m5 326915SN/Afrom m5.objects import * 336915SN/Afrom m5.defines import buildEnv 3412065Snikos.nikoleris@arm.comfrom Ruby import create_topology, create_directories 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366915SN/A 376915SN/A# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396915SN/A# 4011019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4111019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 426915SN/A 437538SN/Adef define_options(parser): 447538SN/A return 457538SN/A 4610519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 4710007Snilay@cs.wisc.edu 4810007Snilay@cs.wisc.edu if buildEnv['PROTOCOL'] != 'MESI_Two_Level': 4910007Snilay@cs.wisc.edu fatal("This script requires the MESI_Two_Level protocol to be built.") 506915SN/A 516915SN/A cpu_sequencers = [] 5210007Snilay@cs.wisc.edu 536915SN/A # 546915SN/A # The ruby network creation expects the list of nodes in the system to be 556915SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 566915SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 576915SN/A # 586915SN/A l1_cntrl_nodes = [] 596915SN/A l2_cntrl_nodes = [] 606915SN/A dma_cntrl_nodes = [] 616915SN/A 626915SN/A # 636915SN/A # Must create the individual controllers before the network to ensure the 646915SN/A # controller constructors are called before the network constructor 656915SN/A # 668180SN/A l2_bits = int(math.log(options.num_l2caches, 2)) 678180SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 6810007Snilay@cs.wisc.edu 696915SN/A for i in xrange(options.num_cpus): 706915SN/A # 716915SN/A # First create the Ruby objects associated with this cpu 726915SN/A # 736915SN/A l1i_cache = L1Cache(size = options.l1i_size, 748180SN/A assoc = options.l1i_assoc, 759319SN/A start_index_bit = block_size_bits, 769319SN/A is_icache = True) 776915SN/A l1d_cache = L1Cache(size = options.l1d_size, 788180SN/A assoc = options.l1d_assoc, 799319SN/A start_index_bit = block_size_bits, 809319SN/A is_icache = False) 816915SN/A 829366SN/A prefetcher = RubyPrefetcher.Prefetcher() 839366SN/A 8411266SBrad.Beckmann@amd.com # the ruby random tester reuses num_cpus to specify the 8511266SBrad.Beckmann@amd.com # number of cpu ports connected to the tester object, which 8611266SBrad.Beckmann@amd.com # is stored in system.cpu. because there is only ever one 8711266SBrad.Beckmann@amd.com # tester object, num_cpus is not necessarily equal to the 8811266SBrad.Beckmann@amd.com # size of system.cpu; therefore if len(system.cpu) == 1 8911266SBrad.Beckmann@amd.com # we use system.cpu[0] to set the clk_domain, thereby ensuring 9011266SBrad.Beckmann@amd.com # we don't index off the end of the cpu list. 9111266SBrad.Beckmann@amd.com if len(system.cpu) == 1: 9211266SBrad.Beckmann@amd.com clk_domain = system.cpu[0].clk_domain 9311266SBrad.Beckmann@amd.com else: 9411266SBrad.Beckmann@amd.com clk_domain = system.cpu[i].clk_domain 9511266SBrad.Beckmann@amd.com 9611266SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, 979696SN/A L1Dcache = l1d_cache, 988436SN/A l2_select_num_bits = l2_bits, 9910529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 1009366SN/A prefetcher = prefetcher, 1019366SN/A ruby_system = ruby_system, 10211266SBrad.Beckmann@amd.com clk_domain = clk_domain, 10311266SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 1049366SN/A enable_prefetch = False) 1058322SN/A 10611266SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, icache = l1i_cache, 10711266SBrad.Beckmann@amd.com dcache = l1d_cache, clk_domain = clk_domain, 1088436SN/A ruby_system = ruby_system) 1096915SN/A 11011266SBrad.Beckmann@amd.com 1118322SN/A l1_cntrl.sequencer = cpu_seq 1129468SN/A exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 11310007Snilay@cs.wisc.edu 1146915SN/A # Add controllers and sequencers to the appropriate lists 1156915SN/A cpu_sequencers.append(cpu_seq) 1166915SN/A l1_cntrl_nodes.append(l1_cntrl) 11710007Snilay@cs.wisc.edu 11810311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 11911022Sjthestness@gmail.com l1_cntrl.mandatoryQueue = MessageBuffer() 12011022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache = MessageBuffer() 12111022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 12211022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache = MessageBuffer() 12311022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 12411022Sjthestness@gmail.com l1_cntrl.unblockFromL1Cache = MessageBuffer() 12511022Sjthestness@gmail.com l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave 12610311Snilay@cs.wisc.edu 12711022Sjthestness@gmail.com l1_cntrl.optionalQueue = MessageBuffer() 12811022Sjthestness@gmail.com 12911022Sjthestness@gmail.com l1_cntrl.requestToL1Cache = MessageBuffer() 13011022Sjthestness@gmail.com l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 13111022Sjthestness@gmail.com l1_cntrl.responseToL1Cache = MessageBuffer() 13211022Sjthestness@gmail.com l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 13310311Snilay@cs.wisc.edu 13410311Snilay@cs.wisc.edu 1358180SN/A l2_index_start = block_size_bits + l2_bits 1368180SN/A 1376915SN/A for i in xrange(options.num_l2caches): 1386915SN/A # 1396915SN/A # First create the Ruby objects associated with this cpu 1406915SN/A # 1416915SN/A l2_cache = L2Cache(size = options.l2_size, 1428180SN/A assoc = options.l2_assoc, 1438180SN/A start_index_bit = l2_index_start) 1446915SN/A 1456915SN/A l2_cntrl = L2Cache_Controller(version = i, 1469696SN/A L2cache = l2_cache, 14711266SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 1488436SN/A ruby_system = ruby_system) 14910007Snilay@cs.wisc.edu 1509468SN/A exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1516915SN/A l2_cntrl_nodes.append(l2_cntrl) 15210007Snilay@cs.wisc.edu 15310311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 15411022Sjthestness@gmail.com l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 15511022Sjthestness@gmail.com l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 15611022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 15711022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 15811022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache = MessageBuffer() 15911022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 16010311Snilay@cs.wisc.edu 16111022Sjthestness@gmail.com l2_cntrl.unblockToL2Cache = MessageBuffer() 16211022Sjthestness@gmail.com l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master 16311022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache = MessageBuffer() 16411022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 16511022Sjthestness@gmail.com l2_cntrl.responseToL2Cache = MessageBuffer() 16611022Sjthestness@gmail.com l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 16710311Snilay@cs.wisc.edu 16810311Snilay@cs.wisc.edu 1699793SN/A # Run each of the ruby memory controllers at a ratio of the frequency of 1709793SN/A # the ruby system 1719793SN/A # clk_divider value is a fix to pass regression. 1729793SN/A ruby_system.memctrl_clk_domain = DerivedClockDomain( 17311266SBrad.Beckmann@amd.com clk_domain = ruby_system.clk_domain, 17411266SBrad.Beckmann@amd.com clk_divider = 3) 1759793SN/A 17612065Snikos.nikoleris@arm.com dir_cntrl_nodes = create_directories(options, system.mem_ranges, 17712065Snikos.nikoleris@arm.com ruby_system) 17812065Snikos.nikoleris@arm.com for dir_cntrl in dir_cntrl_nodes: 17910311Snilay@cs.wisc.edu # Connect the directory controllers and the network 18011022Sjthestness@gmail.com dir_cntrl.requestToDir = MessageBuffer() 18111022Sjthestness@gmail.com dir_cntrl.requestToDir.slave = ruby_system.network.master 18211022Sjthestness@gmail.com dir_cntrl.responseToDir = MessageBuffer() 18311022Sjthestness@gmail.com dir_cntrl.responseToDir.slave = ruby_system.network.master 18411022Sjthestness@gmail.com dir_cntrl.responseFromDir = MessageBuffer() 18511022Sjthestness@gmail.com dir_cntrl.responseFromDir.master = ruby_system.network.slave 18611022Sjthestness@gmail.com dir_cntrl.responseFromMemory = MessageBuffer() 18710311Snilay@cs.wisc.edu 18810311Snilay@cs.wisc.edu 1898929SN/A for i, dma_port in enumerate(dma_ports): 1906915SN/A # Create the Ruby objects associated with the dma controller 19111266SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, ruby_system = ruby_system, 19210519Snilay@cs.wisc.edu slave = dma_port) 19310007Snilay@cs.wisc.edu 19411266SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, 1959841SN/A transitions_per_cycle = options.ports, 1968477SN/A ruby_system = ruby_system) 1976915SN/A 1989468SN/A exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 1996915SN/A dma_cntrl_nodes.append(dma_cntrl) 2008257SN/A 20110311Snilay@cs.wisc.edu # Connect the dma controller to the network 20211022Sjthestness@gmail.com dma_cntrl.mandatoryQueue = MessageBuffer() 20311022Sjthestness@gmail.com dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 20411022Sjthestness@gmail.com dma_cntrl.responseFromDir.slave = ruby_system.network.master 20511022Sjthestness@gmail.com dma_cntrl.requestToDir = MessageBuffer() 20611022Sjthestness@gmail.com dma_cntrl.requestToDir.master = ruby_system.network.slave 20710311Snilay@cs.wisc.edu 2086915SN/A all_cntrls = l1_cntrl_nodes + \ 2096915SN/A l2_cntrl_nodes + \ 2106915SN/A dir_cntrl_nodes + \ 2116915SN/A dma_cntrl_nodes 2126915SN/A 21310519Snilay@cs.wisc.edu # Create the io controller and the sequencer 21410519Snilay@cs.wisc.edu if full_system: 21511266SBrad.Beckmann@amd.com io_seq = DMASequencer(version = len(dma_ports), 21611266SBrad.Beckmann@amd.com ruby_system = ruby_system) 21710519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 21810519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 21910519Snilay@cs.wisc.edu dma_sequencer = io_seq, 22010519Snilay@cs.wisc.edu ruby_system = ruby_system) 22110519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 22210519Snilay@cs.wisc.edu 22310519Snilay@cs.wisc.edu # Connect the dma controller to the network 22411022Sjthestness@gmail.com io_controller.mandatoryQueue = MessageBuffer() 22511022Sjthestness@gmail.com io_controller.responseFromDir = MessageBuffer(ordered = True) 22611022Sjthestness@gmail.com io_controller.responseFromDir.slave = ruby_system.network.master 22711022Sjthestness@gmail.com io_controller.requestToDir = MessageBuffer() 22811022Sjthestness@gmail.com io_controller.requestToDir.master = ruby_system.network.slave 22910519Snilay@cs.wisc.edu 23010519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 23110519Snilay@cs.wisc.edu 23211065Snilay@cs.wisc.edu ruby_system.network.number_of_virtual_networks = 3 2339100SN/A topology = create_topology(all_cntrls, options) 2349100SN/A return (cpu_sequencers, dir_cntrl_nodes, topology) 235