MESI_Two_Level.py revision 11266
16915SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26915SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 36915SN/A# All rights reserved. 46915SN/A# 56915SN/A# Redistribution and use in source and binary forms, with or without 66915SN/A# modification, are permitted provided that the following conditions are 76915SN/A# met: redistributions of source code must retain the above copyright 86915SN/A# notice, this list of conditions and the following disclaimer; 96915SN/A# redistributions in binary form must reproduce the above copyright 106915SN/A# notice, this list of conditions and the following disclaimer in the 116915SN/A# documentation and/or other materials provided with the distribution; 126915SN/A# neither the name of the copyright holders nor the names of its 136915SN/A# contributors may be used to endorse or promote products derived from 146915SN/A# this software without specific prior written permission. 156915SN/A# 166915SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176915SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186915SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196915SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206915SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216915SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226915SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236915SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246915SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256915SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266915SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276915SN/A# 286915SN/A# Authors: Brad Beckmann 296915SN/A 306915SN/Aimport math 316915SN/Aimport m5 326915SN/Afrom m5.objects import * 336915SN/Afrom m5.defines import buildEnv 349100SN/Afrom Ruby import create_topology 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366915SN/A 376915SN/A# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396915SN/A# 4011019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4111019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 426915SN/A 437538SN/Adef define_options(parser): 447538SN/A return 457538SN/A 4610519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 4710007Snilay@cs.wisc.edu 4810007Snilay@cs.wisc.edu if buildEnv['PROTOCOL'] != 'MESI_Two_Level': 4910007Snilay@cs.wisc.edu fatal("This script requires the MESI_Two_Level protocol to be built.") 506915SN/A 516915SN/A cpu_sequencers = [] 5210007Snilay@cs.wisc.edu 536915SN/A # 546915SN/A # The ruby network creation expects the list of nodes in the system to be 556915SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 566915SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 576915SN/A # 586915SN/A l1_cntrl_nodes = [] 596915SN/A l2_cntrl_nodes = [] 606915SN/A dir_cntrl_nodes = [] 616915SN/A dma_cntrl_nodes = [] 626915SN/A 636915SN/A # 646915SN/A # Must create the individual controllers before the network to ensure the 656915SN/A # controller constructors are called before the network constructor 666915SN/A # 678180SN/A l2_bits = int(math.log(options.num_l2caches, 2)) 688180SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 6910007Snilay@cs.wisc.edu 706915SN/A for i in xrange(options.num_cpus): 716915SN/A # 726915SN/A # First create the Ruby objects associated with this cpu 736915SN/A # 746915SN/A l1i_cache = L1Cache(size = options.l1i_size, 758180SN/A assoc = options.l1i_assoc, 769319SN/A start_index_bit = block_size_bits, 779319SN/A is_icache = True) 786915SN/A l1d_cache = L1Cache(size = options.l1d_size, 798180SN/A assoc = options.l1d_assoc, 809319SN/A start_index_bit = block_size_bits, 819319SN/A is_icache = False) 826915SN/A 839366SN/A prefetcher = RubyPrefetcher.Prefetcher() 849366SN/A 8511266SBrad.Beckmann@amd.com # the ruby random tester reuses num_cpus to specify the 8611266SBrad.Beckmann@amd.com # number of cpu ports connected to the tester object, which 8711266SBrad.Beckmann@amd.com # is stored in system.cpu. because there is only ever one 8811266SBrad.Beckmann@amd.com # tester object, num_cpus is not necessarily equal to the 8911266SBrad.Beckmann@amd.com # size of system.cpu; therefore if len(system.cpu) == 1 9011266SBrad.Beckmann@amd.com # we use system.cpu[0] to set the clk_domain, thereby ensuring 9111266SBrad.Beckmann@amd.com # we don't index off the end of the cpu list. 9211266SBrad.Beckmann@amd.com if len(system.cpu) == 1: 9311266SBrad.Beckmann@amd.com clk_domain = system.cpu[0].clk_domain 9411266SBrad.Beckmann@amd.com else: 9511266SBrad.Beckmann@amd.com clk_domain = system.cpu[i].clk_domain 9611266SBrad.Beckmann@amd.com 9711266SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, 989696SN/A L1Dcache = l1d_cache, 998436SN/A l2_select_num_bits = l2_bits, 10010529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 1019366SN/A prefetcher = prefetcher, 1029366SN/A ruby_system = ruby_system, 10311266SBrad.Beckmann@amd.com clk_domain = clk_domain, 10411266SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 1059366SN/A enable_prefetch = False) 1068322SN/A 10711266SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, icache = l1i_cache, 10811266SBrad.Beckmann@amd.com dcache = l1d_cache, clk_domain = clk_domain, 1098436SN/A ruby_system = ruby_system) 1106915SN/A 11111266SBrad.Beckmann@amd.com 1128322SN/A l1_cntrl.sequencer = cpu_seq 1139468SN/A exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 11410007Snilay@cs.wisc.edu 1156915SN/A # Add controllers and sequencers to the appropriate lists 1166915SN/A cpu_sequencers.append(cpu_seq) 1176915SN/A l1_cntrl_nodes.append(l1_cntrl) 11810007Snilay@cs.wisc.edu 11910311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 12011022Sjthestness@gmail.com l1_cntrl.mandatoryQueue = MessageBuffer() 12111022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache = MessageBuffer() 12211022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 12311022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache = MessageBuffer() 12411022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 12511022Sjthestness@gmail.com l1_cntrl.unblockFromL1Cache = MessageBuffer() 12611022Sjthestness@gmail.com l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave 12710311Snilay@cs.wisc.edu 12811022Sjthestness@gmail.com l1_cntrl.optionalQueue = MessageBuffer() 12911022Sjthestness@gmail.com 13011022Sjthestness@gmail.com l1_cntrl.requestToL1Cache = MessageBuffer() 13111022Sjthestness@gmail.com l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 13211022Sjthestness@gmail.com l1_cntrl.responseToL1Cache = MessageBuffer() 13311022Sjthestness@gmail.com l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 13410311Snilay@cs.wisc.edu 13510311Snilay@cs.wisc.edu 1368180SN/A l2_index_start = block_size_bits + l2_bits 1378180SN/A 1386915SN/A for i in xrange(options.num_l2caches): 1396915SN/A # 1406915SN/A # First create the Ruby objects associated with this cpu 1416915SN/A # 1426915SN/A l2_cache = L2Cache(size = options.l2_size, 1438180SN/A assoc = options.l2_assoc, 1448180SN/A start_index_bit = l2_index_start) 1456915SN/A 1466915SN/A l2_cntrl = L2Cache_Controller(version = i, 1479696SN/A L2cache = l2_cache, 14811266SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 1498436SN/A ruby_system = ruby_system) 15010007Snilay@cs.wisc.edu 1519468SN/A exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1526915SN/A l2_cntrl_nodes.append(l2_cntrl) 15310007Snilay@cs.wisc.edu 15410311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 15511022Sjthestness@gmail.com l2_cntrl.DirRequestFromL2Cache = MessageBuffer() 15611022Sjthestness@gmail.com l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave 15711022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 15811022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 15911022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache = MessageBuffer() 16011022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 16110311Snilay@cs.wisc.edu 16211022Sjthestness@gmail.com l2_cntrl.unblockToL2Cache = MessageBuffer() 16311022Sjthestness@gmail.com l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master 16411022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache = MessageBuffer() 16511022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 16611022Sjthestness@gmail.com l2_cntrl.responseToL2Cache = MessageBuffer() 16711022Sjthestness@gmail.com l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 16810311Snilay@cs.wisc.edu 16910311Snilay@cs.wisc.edu 1709826SN/A phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1719798SN/A assert(phys_mem_size % options.num_dirs == 0) 1726915SN/A mem_module_size = phys_mem_size / options.num_dirs 1736915SN/A 17410311Snilay@cs.wisc.edu 1759793SN/A # Run each of the ruby memory controllers at a ratio of the frequency of 1769793SN/A # the ruby system 1779793SN/A # clk_divider value is a fix to pass regression. 1789793SN/A ruby_system.memctrl_clk_domain = DerivedClockDomain( 17911266SBrad.Beckmann@amd.com clk_domain = ruby_system.clk_domain, 18011266SBrad.Beckmann@amd.com clk_divider = 3) 1819793SN/A 1826915SN/A for i in xrange(options.num_dirs): 1836915SN/A dir_size = MemorySize('0B') 1846915SN/A dir_size.value = mem_module_size 1856915SN/A 1866915SN/A dir_cntrl = Directory_Controller(version = i, 18711266SBrad.Beckmann@amd.com directory = RubyDirectoryMemory(version = i, size = dir_size), 18811266SBrad.Beckmann@amd.com transitions_per_cycle = options.ports, 18911266SBrad.Beckmann@amd.com ruby_system = ruby_system) 1906915SN/A 1919468SN/A exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1926915SN/A dir_cntrl_nodes.append(dir_cntrl) 1936915SN/A 19410311Snilay@cs.wisc.edu # Connect the directory controllers and the network 19511022Sjthestness@gmail.com dir_cntrl.requestToDir = MessageBuffer() 19611022Sjthestness@gmail.com dir_cntrl.requestToDir.slave = ruby_system.network.master 19711022Sjthestness@gmail.com dir_cntrl.responseToDir = MessageBuffer() 19811022Sjthestness@gmail.com dir_cntrl.responseToDir.slave = ruby_system.network.master 19911022Sjthestness@gmail.com dir_cntrl.responseFromDir = MessageBuffer() 20011022Sjthestness@gmail.com dir_cntrl.responseFromDir.master = ruby_system.network.slave 20111022Sjthestness@gmail.com dir_cntrl.responseFromMemory = MessageBuffer() 20210311Snilay@cs.wisc.edu 20310311Snilay@cs.wisc.edu 2048929SN/A for i, dma_port in enumerate(dma_ports): 2056915SN/A # Create the Ruby objects associated with the dma controller 20611266SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, ruby_system = ruby_system, 20710519Snilay@cs.wisc.edu slave = dma_port) 20810007Snilay@cs.wisc.edu 20911266SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, 2109841SN/A transitions_per_cycle = options.ports, 2118477SN/A ruby_system = ruby_system) 2126915SN/A 2139468SN/A exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2146915SN/A dma_cntrl_nodes.append(dma_cntrl) 2158257SN/A 21610311Snilay@cs.wisc.edu # Connect the dma controller to the network 21711022Sjthestness@gmail.com dma_cntrl.mandatoryQueue = MessageBuffer() 21811022Sjthestness@gmail.com dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 21911022Sjthestness@gmail.com dma_cntrl.responseFromDir.slave = ruby_system.network.master 22011022Sjthestness@gmail.com dma_cntrl.requestToDir = MessageBuffer() 22111022Sjthestness@gmail.com dma_cntrl.requestToDir.master = ruby_system.network.slave 22210311Snilay@cs.wisc.edu 2236915SN/A all_cntrls = l1_cntrl_nodes + \ 2246915SN/A l2_cntrl_nodes + \ 2256915SN/A dir_cntrl_nodes + \ 2266915SN/A dma_cntrl_nodes 2276915SN/A 22810519Snilay@cs.wisc.edu # Create the io controller and the sequencer 22910519Snilay@cs.wisc.edu if full_system: 23011266SBrad.Beckmann@amd.com io_seq = DMASequencer(version = len(dma_ports), 23111266SBrad.Beckmann@amd.com ruby_system = ruby_system) 23210519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 23310519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 23410519Snilay@cs.wisc.edu dma_sequencer = io_seq, 23510519Snilay@cs.wisc.edu ruby_system = ruby_system) 23610519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 23710519Snilay@cs.wisc.edu 23810519Snilay@cs.wisc.edu # Connect the dma controller to the network 23911022Sjthestness@gmail.com io_controller.mandatoryQueue = MessageBuffer() 24011022Sjthestness@gmail.com io_controller.responseFromDir = MessageBuffer(ordered = True) 24111022Sjthestness@gmail.com io_controller.responseFromDir.slave = ruby_system.network.master 24211022Sjthestness@gmail.com io_controller.requestToDir = MessageBuffer() 24311022Sjthestness@gmail.com io_controller.requestToDir.master = ruby_system.network.slave 24410519Snilay@cs.wisc.edu 24510519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 24610519Snilay@cs.wisc.edu 24711065Snilay@cs.wisc.edu ruby_system.network.number_of_virtual_networks = 3 2489100SN/A topology = create_topology(all_cntrls, options) 2499100SN/A return (cpu_sequencers, dir_cntrl_nodes, topology) 250