MESI_Two_Level.py revision 10311
16915SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26915SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 36915SN/A# All rights reserved. 46915SN/A# 56915SN/A# Redistribution and use in source and binary forms, with or without 66915SN/A# modification, are permitted provided that the following conditions are 76915SN/A# met: redistributions of source code must retain the above copyright 86915SN/A# notice, this list of conditions and the following disclaimer; 96915SN/A# redistributions in binary form must reproduce the above copyright 106915SN/A# notice, this list of conditions and the following disclaimer in the 116915SN/A# documentation and/or other materials provided with the distribution; 126915SN/A# neither the name of the copyright holders nor the names of its 136915SN/A# contributors may be used to endorse or promote products derived from 146915SN/A# this software without specific prior written permission. 156915SN/A# 166915SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176915SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186915SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196915SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206915SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216915SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226915SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236915SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246915SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256915SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266915SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276915SN/A# 286915SN/A# Authors: Brad Beckmann 296915SN/A 306915SN/Aimport math 316915SN/Aimport m5 326915SN/Afrom m5.objects import * 336915SN/Afrom m5.defines import buildEnv 349100SN/Afrom Ruby import create_topology 356915SN/A 366915SN/A# 376915SN/A# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386915SN/A# 396915SN/Aclass L1Cache(RubyCache): 406915SN/A latency = 3 416915SN/A 426915SN/A# 436915SN/A# Note: the L2 Cache latency is not currently used 446915SN/A# 456915SN/Aclass L2Cache(RubyCache): 466915SN/A latency = 15 476915SN/A 487538SN/Adef define_options(parser): 497538SN/A return 507538SN/A 5110116Snilay@cs.wisc.edudef create_system(options, system, dma_ports, ruby_system): 5210007Snilay@cs.wisc.edu 5310007Snilay@cs.wisc.edu if buildEnv['PROTOCOL'] != 'MESI_Two_Level': 5410007Snilay@cs.wisc.edu fatal("This script requires the MESI_Two_Level protocol to be built.") 556915SN/A 566915SN/A cpu_sequencers = [] 5710007Snilay@cs.wisc.edu 586915SN/A # 596915SN/A # The ruby network creation expects the list of nodes in the system to be 606915SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 616915SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 626915SN/A # 636915SN/A l1_cntrl_nodes = [] 646915SN/A l2_cntrl_nodes = [] 656915SN/A dir_cntrl_nodes = [] 666915SN/A dma_cntrl_nodes = [] 676915SN/A 686915SN/A # 696915SN/A # Must create the individual controllers before the network to ensure the 706915SN/A # controller constructors are called before the network constructor 716915SN/A # 728180SN/A l2_bits = int(math.log(options.num_l2caches, 2)) 738180SN/A block_size_bits = int(math.log(options.cacheline_size, 2)) 7410007Snilay@cs.wisc.edu 756915SN/A for i in xrange(options.num_cpus): 766915SN/A # 776915SN/A # First create the Ruby objects associated with this cpu 786915SN/A # 796915SN/A l1i_cache = L1Cache(size = options.l1i_size, 808180SN/A assoc = options.l1i_assoc, 819319SN/A start_index_bit = block_size_bits, 829319SN/A is_icache = True) 836915SN/A l1d_cache = L1Cache(size = options.l1d_size, 848180SN/A assoc = options.l1d_assoc, 859319SN/A start_index_bit = block_size_bits, 869319SN/A is_icache = False) 876915SN/A 889366SN/A prefetcher = RubyPrefetcher.Prefetcher() 899366SN/A 908322SN/A l1_cntrl = L1Cache_Controller(version = i, 919696SN/A L1Icache = l1i_cache, 929696SN/A L1Dcache = l1d_cache, 938436SN/A l2_select_num_bits = l2_bits, 948717SN/A send_evictions = ( 958717SN/A options.cpu_type == "detailed"), 969366SN/A prefetcher = prefetcher, 979366SN/A ruby_system = ruby_system, 9810300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 999841SN/A transitions_per_cycle=options.ports, 1009366SN/A enable_prefetch = False) 1018322SN/A 1027015SN/A cpu_seq = RubySequencer(version = i, 1037015SN/A icache = l1i_cache, 1046915SN/A dcache = l1d_cache, 10510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 1068436SN/A ruby_system = ruby_system) 1076915SN/A 1088322SN/A l1_cntrl.sequencer = cpu_seq 1099468SN/A exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 11010007Snilay@cs.wisc.edu 1116915SN/A # Add controllers and sequencers to the appropriate lists 1126915SN/A cpu_sequencers.append(cpu_seq) 1136915SN/A l1_cntrl_nodes.append(l1_cntrl) 11410007Snilay@cs.wisc.edu 11510311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 11610311Snilay@cs.wisc.edu l1_cntrl.requestFromL1Cache = ruby_system.network.slave 11710311Snilay@cs.wisc.edu l1_cntrl.responseFromL1Cache = ruby_system.network.slave 11810311Snilay@cs.wisc.edu l1_cntrl.unblockFromL1Cache = ruby_system.network.slave 11910311Snilay@cs.wisc.edu 12010311Snilay@cs.wisc.edu l1_cntrl.requestToL1Cache = ruby_system.network.master 12110311Snilay@cs.wisc.edu l1_cntrl.responseToL1Cache = ruby_system.network.master 12210311Snilay@cs.wisc.edu 12310311Snilay@cs.wisc.edu 1248180SN/A l2_index_start = block_size_bits + l2_bits 1258180SN/A 1266915SN/A for i in xrange(options.num_l2caches): 1276915SN/A # 1286915SN/A # First create the Ruby objects associated with this cpu 1296915SN/A # 1306915SN/A l2_cache = L2Cache(size = options.l2_size, 1318180SN/A assoc = options.l2_assoc, 1328180SN/A start_index_bit = l2_index_start) 1336915SN/A 1346915SN/A l2_cntrl = L2Cache_Controller(version = i, 1359696SN/A L2cache = l2_cache, 1369841SN/A transitions_per_cycle=options.ports, 1378436SN/A ruby_system = ruby_system) 13810007Snilay@cs.wisc.edu 1399468SN/A exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1406915SN/A l2_cntrl_nodes.append(l2_cntrl) 14110007Snilay@cs.wisc.edu 14210311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 14310311Snilay@cs.wisc.edu l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 14410311Snilay@cs.wisc.edu l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 14510311Snilay@cs.wisc.edu l2_cntrl.responseFromL2Cache = ruby_system.network.slave 14610311Snilay@cs.wisc.edu 14710311Snilay@cs.wisc.edu l2_cntrl.unblockToL2Cache = ruby_system.network.master 14810311Snilay@cs.wisc.edu l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 14910311Snilay@cs.wisc.edu l2_cntrl.responseToL2Cache = ruby_system.network.master 15010311Snilay@cs.wisc.edu 15110311Snilay@cs.wisc.edu 1529826SN/A phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1539798SN/A assert(phys_mem_size % options.num_dirs == 0) 1546915SN/A mem_module_size = phys_mem_size / options.num_dirs 1556915SN/A 15610311Snilay@cs.wisc.edu 1579793SN/A # Run each of the ruby memory controllers at a ratio of the frequency of 1589793SN/A # the ruby system 1599793SN/A # clk_divider value is a fix to pass regression. 1609793SN/A ruby_system.memctrl_clk_domain = DerivedClockDomain( 1619793SN/A clk_domain=ruby_system.clk_domain, 1629793SN/A clk_divider=3) 1639793SN/A 1646915SN/A for i in xrange(options.num_dirs): 1656915SN/A # 1666915SN/A # Create the Ruby objects associated with the directory controller 1676915SN/A # 1686915SN/A 1699793SN/A mem_cntrl = RubyMemoryControl( 1709793SN/A clk_domain = ruby_system.memctrl_clk_domain, 1719793SN/A version = i, 1729793SN/A ruby_system = ruby_system) 1736915SN/A 1746915SN/A dir_size = MemorySize('0B') 1756915SN/A dir_size.value = mem_module_size 1766915SN/A 1776915SN/A dir_cntrl = Directory_Controller(version = i, 1786915SN/A directory = \ 1796915SN/A RubyDirectoryMemory(version = i, 1808718SN/A size = dir_size, 1818718SN/A use_map = 1828718SN/A options.use_map), 1838436SN/A memBuffer = mem_cntrl, 1849841SN/A transitions_per_cycle = options.ports, 1858436SN/A ruby_system = ruby_system) 1866915SN/A 1879468SN/A exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1886915SN/A dir_cntrl_nodes.append(dir_cntrl) 1896915SN/A 19010311Snilay@cs.wisc.edu # Connect the directory controllers and the network 19110311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 19210311Snilay@cs.wisc.edu dir_cntrl.responseToDir = ruby_system.network.master 19310311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 19410311Snilay@cs.wisc.edu 19510311Snilay@cs.wisc.edu 1968929SN/A for i, dma_port in enumerate(dma_ports): 1976915SN/A # Create the Ruby objects associated with the dma controller 1986915SN/A dma_seq = DMASequencer(version = i, 1998477SN/A ruby_system = ruby_system) 20010007Snilay@cs.wisc.edu 2016915SN/A dma_cntrl = DMA_Controller(version = i, 2028477SN/A dma_sequencer = dma_seq, 2039841SN/A transitions_per_cycle = options.ports, 2048477SN/A ruby_system = ruby_system) 2056915SN/A 2069468SN/A exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2079468SN/A exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 2086915SN/A dma_cntrl_nodes.append(dma_cntrl) 2098257SN/A 21010311Snilay@cs.wisc.edu # Connect the dma controller to the network 21110311Snilay@cs.wisc.edu dma_cntrl.responseFromDir = ruby_system.network.master 21210311Snilay@cs.wisc.edu dma_cntrl.requestToDir = ruby_system.network.slave 21310311Snilay@cs.wisc.edu 21410311Snilay@cs.wisc.edu 2156915SN/A all_cntrls = l1_cntrl_nodes + \ 2166915SN/A l2_cntrl_nodes + \ 2176915SN/A dir_cntrl_nodes + \ 2186915SN/A dma_cntrl_nodes 2196915SN/A 2209100SN/A topology = create_topology(all_cntrls, options) 2219100SN/A 2229100SN/A return (cpu_sequencers, dir_cntrl_nodes, topology) 223