MESI_Three_Level.py revision 11019:fc1e41e88fd3
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Brad Beckmann 30# Nilay Vaish 31 32import math 33import m5 34from m5.objects import * 35from m5.defines import buildEnv 36from Ruby import create_topology 37from Ruby import send_evicts 38 39# 40# Declare caches used by the protocol 41# 42class L0Cache(RubyCache): pass 43class L1Cache(RubyCache): pass 44class L2Cache(RubyCache): pass 45 46def define_options(parser): 47 parser.add_option("--num-clusters", type="int", default=1, 48 help="number of clusters in a design in which there are shared\ 49 caches private to clusters") 50 return 51 52def create_system(options, full_system, system, dma_ports, ruby_system): 53 54 if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 55 fatal("This script requires the MESI_Three_Level protocol to be built.") 56 57 cpu_sequencers = [] 58 59 # 60 # The ruby network creation expects the list of nodes in the system to be 61 # consistent with the NetDest list. Therefore the l1 controller nodes must be 62 # listed before the directory nodes and directory nodes before dma nodes, etc. 63 # 64 l0_cntrl_nodes = [] 65 l1_cntrl_nodes = [] 66 l2_cntrl_nodes = [] 67 dir_cntrl_nodes = [] 68 dma_cntrl_nodes = [] 69 70 assert (options.num_cpus % options.num_clusters == 0) 71 num_cpus_per_cluster = options.num_cpus / options.num_clusters 72 73 assert (options.num_l2caches % options.num_clusters == 0) 74 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 75 76 l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 77 block_size_bits = int(math.log(options.cacheline_size, 2)) 78 l2_index_start = block_size_bits + l2_bits 79 80 # 81 # Must create the individual controllers before the network to ensure the 82 # controller constructors are called before the network constructor 83 # 84 for i in xrange(options.num_clusters): 85 for j in xrange(num_cpus_per_cluster): 86 # 87 # First create the Ruby objects associated with this cpu 88 # 89 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 90 start_index_bit = block_size_bits, 91 replacement_policy = LRUReplacementPolicy()) 92 93 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 94 start_index_bit = block_size_bits, 95 replacement_policy = LRUReplacementPolicy()) 96 97 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 98 Icache = l0i_cache, Dcache = l0d_cache, 99 send_evictions = send_evicts(options), 100 clk_domain=system.cpu[i].clk_domain, 101 ruby_system = ruby_system) 102 103 cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j, 104 icache = l0i_cache, 105 clk_domain=system.cpu[i].clk_domain, 106 dcache = l0d_cache, ruby_system = ruby_system) 107 108 l0_cntrl.sequencer = cpu_seq 109 110 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 111 start_index_bit = block_size_bits, is_icache = False) 112 113 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 114 cache = l1_cache, l2_select_num_bits = l2_bits, 115 cluster_id = i, ruby_system = ruby_system) 116 117 exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 118 i*num_cpus_per_cluster+j)) 119 exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 120 i*num_cpus_per_cluster+j)) 121 122 # 123 # Add controllers and sequencers to the appropriate lists 124 # 125 cpu_sequencers.append(cpu_seq) 126 l0_cntrl_nodes.append(l0_cntrl) 127 l1_cntrl_nodes.append(l1_cntrl) 128 129 # Connect the L0 and L1 controllers 130 l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0 131 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0 132 133 # Connect the L1 controllers and the network 134 l1_cntrl.requestToL2 = ruby_system.network.slave 135 l1_cntrl.responseToL2 = ruby_system.network.slave 136 l1_cntrl.unblockToL2 = ruby_system.network.slave 137 138 l1_cntrl.requestFromL2 = ruby_system.network.master 139 l1_cntrl.responseFromL2 = ruby_system.network.master 140 141 142 for j in xrange(num_l2caches_per_cluster): 143 l2_cache = L2Cache(size = options.l2_size, 144 assoc = options.l2_assoc, 145 start_index_bit = l2_index_start) 146 147 l2_cntrl = L2Cache_Controller( 148 version = i * num_l2caches_per_cluster + j, 149 L2cache = l2_cache, cluster_id = i, 150 transitions_per_cycle=options.ports, 151 ruby_system = ruby_system) 152 153 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 154 i * num_l2caches_per_cluster + j)) 155 l2_cntrl_nodes.append(l2_cntrl) 156 157 # Connect the L2 controllers and the network 158 l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 159 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 160 l2_cntrl.responseFromL2Cache = ruby_system.network.slave 161 162 l2_cntrl.unblockToL2Cache = ruby_system.network.master 163 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 164 l2_cntrl.responseToL2Cache = ruby_system.network.master 165 166 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 167 assert(phys_mem_size % options.num_dirs == 0) 168 mem_module_size = phys_mem_size / options.num_dirs 169 170 # Run each of the ruby memory controllers at a ratio of the frequency of 171 # the ruby system 172 # clk_divider value is a fix to pass regression. 173 ruby_system.memctrl_clk_domain = DerivedClockDomain( 174 clk_domain=ruby_system.clk_domain, 175 clk_divider=3) 176 177 for i in xrange(options.num_dirs): 178 # 179 # Create the Ruby objects associated with the directory controller 180 # 181 dir_size = MemorySize('0B') 182 dir_size.value = mem_module_size 183 184 dir_cntrl = Directory_Controller(version = i, 185 directory = RubyDirectoryMemory( 186 version = i, size = dir_size), 187 transitions_per_cycle = options.ports, 188 ruby_system = ruby_system) 189 190 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 191 dir_cntrl_nodes.append(dir_cntrl) 192 193 # Connect the directory controllers and the network 194 dir_cntrl.requestToDir = ruby_system.network.master 195 dir_cntrl.responseToDir = ruby_system.network.master 196 dir_cntrl.responseFromDir = ruby_system.network.slave 197 198 for i, dma_port in enumerate(dma_ports): 199 # 200 # Create the Ruby objects associated with the dma controller 201 # 202 dma_seq = DMASequencer(version = i, 203 ruby_system = ruby_system) 204 205 dma_cntrl = DMA_Controller(version = i, 206 dma_sequencer = dma_seq, 207 transitions_per_cycle = options.ports, 208 ruby_system = ruby_system) 209 210 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 211 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 212 dma_cntrl_nodes.append(dma_cntrl) 213 214 # Connect the dma controller to the network 215 dma_cntrl.responseFromDir = ruby_system.network.master 216 dma_cntrl.requestToDir = ruby_system.network.slave 217 218 all_cntrls = l0_cntrl_nodes + \ 219 l1_cntrl_nodes + \ 220 l2_cntrl_nodes + \ 221 dir_cntrl_nodes + \ 222 dma_cntrl_nodes 223 224 # Create the io controller and the sequencer 225 if full_system: 226 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 227 ruby_system._io_port = io_seq 228 io_controller = DMA_Controller(version = len(dma_ports), 229 dma_sequencer = io_seq, 230 ruby_system = ruby_system) 231 ruby_system.io_controller = io_controller 232 233 # Connect the dma controller to the network 234 io_controller.responseFromDir = ruby_system.network.master 235 io_controller.requestToDir = ruby_system.network.slave 236 237 all_cntrls = all_cntrls + [io_controller] 238 239 topology = create_topology(all_cntrls, options) 240 return (cpu_sequencers, dir_cntrl_nodes, topology) 241