MESI_Three_Level.py revision 11019
110008Snilay@cs.wisc.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 210008Snilay@cs.wisc.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 310008Snilay@cs.wisc.edu# Copyright (c) 2013 Mark D. Hill and David A. Wood 410008Snilay@cs.wisc.edu# All rights reserved. 510008Snilay@cs.wisc.edu# 610008Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 710008Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 810008Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 910008Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 1010008Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 1110008Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 1210008Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 1310008Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 1410008Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 1510008Snilay@cs.wisc.edu# this software without specific prior written permission. 1610008Snilay@cs.wisc.edu# 1710008Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810008Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910008Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010008Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110008Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210008Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310008Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410008Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510008Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610008Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710008Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810008Snilay@cs.wisc.edu# 2910008Snilay@cs.wisc.edu# Authors: Brad Beckmann 3010008Snilay@cs.wisc.edu# Nilay Vaish 3110008Snilay@cs.wisc.edu 3210008Snilay@cs.wisc.eduimport math 3310008Snilay@cs.wisc.eduimport m5 3410008Snilay@cs.wisc.edufrom m5.objects import * 3510008Snilay@cs.wisc.edufrom m5.defines import buildEnv 3610008Snilay@cs.wisc.edufrom Ruby import create_topology 3710529Smorr@cs.wisc.edufrom Ruby import send_evicts 3810008Snilay@cs.wisc.edu 3910008Snilay@cs.wisc.edu# 4011019Sjthestness@gmail.com# Declare caches used by the protocol 4110008Snilay@cs.wisc.edu# 4211019Sjthestness@gmail.comclass L0Cache(RubyCache): pass 4311019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4411019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 4510008Snilay@cs.wisc.edu 4610008Snilay@cs.wisc.edudef define_options(parser): 4710008Snilay@cs.wisc.edu parser.add_option("--num-clusters", type="int", default=1, 4810008Snilay@cs.wisc.edu help="number of clusters in a design in which there are shared\ 4910008Snilay@cs.wisc.edu caches private to clusters") 5010008Snilay@cs.wisc.edu return 5110008Snilay@cs.wisc.edu 5210519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 5310008Snilay@cs.wisc.edu 5410008Snilay@cs.wisc.edu if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 5510008Snilay@cs.wisc.edu fatal("This script requires the MESI_Three_Level protocol to be built.") 5610008Snilay@cs.wisc.edu 5710008Snilay@cs.wisc.edu cpu_sequencers = [] 5810008Snilay@cs.wisc.edu 5910008Snilay@cs.wisc.edu # 6010008Snilay@cs.wisc.edu # The ruby network creation expects the list of nodes in the system to be 6110008Snilay@cs.wisc.edu # consistent with the NetDest list. Therefore the l1 controller nodes must be 6210008Snilay@cs.wisc.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 6310008Snilay@cs.wisc.edu # 6410008Snilay@cs.wisc.edu l0_cntrl_nodes = [] 6510008Snilay@cs.wisc.edu l1_cntrl_nodes = [] 6610008Snilay@cs.wisc.edu l2_cntrl_nodes = [] 6710008Snilay@cs.wisc.edu dir_cntrl_nodes = [] 6810008Snilay@cs.wisc.edu dma_cntrl_nodes = [] 6910008Snilay@cs.wisc.edu 7010008Snilay@cs.wisc.edu assert (options.num_cpus % options.num_clusters == 0) 7110008Snilay@cs.wisc.edu num_cpus_per_cluster = options.num_cpus / options.num_clusters 7210008Snilay@cs.wisc.edu 7310008Snilay@cs.wisc.edu assert (options.num_l2caches % options.num_clusters == 0) 7410008Snilay@cs.wisc.edu num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 7510008Snilay@cs.wisc.edu 7610008Snilay@cs.wisc.edu l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 7710008Snilay@cs.wisc.edu block_size_bits = int(math.log(options.cacheline_size, 2)) 7810008Snilay@cs.wisc.edu l2_index_start = block_size_bits + l2_bits 7910008Snilay@cs.wisc.edu 8010008Snilay@cs.wisc.edu # 8110008Snilay@cs.wisc.edu # Must create the individual controllers before the network to ensure the 8210008Snilay@cs.wisc.edu # controller constructors are called before the network constructor 8310008Snilay@cs.wisc.edu # 8410008Snilay@cs.wisc.edu for i in xrange(options.num_clusters): 8510008Snilay@cs.wisc.edu for j in xrange(num_cpus_per_cluster): 8610008Snilay@cs.wisc.edu # 8710008Snilay@cs.wisc.edu # First create the Ruby objects associated with this cpu 8810008Snilay@cs.wisc.edu # 8910008Snilay@cs.wisc.edu l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 9010970Sdavid.hashe@amd.com start_index_bit = block_size_bits, 9110970Sdavid.hashe@amd.com replacement_policy = LRUReplacementPolicy()) 9210008Snilay@cs.wisc.edu 9310008Snilay@cs.wisc.edu l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 9410970Sdavid.hashe@amd.com start_index_bit = block_size_bits, 9510970Sdavid.hashe@amd.com replacement_policy = LRUReplacementPolicy()) 9610008Snilay@cs.wisc.edu 9710008Snilay@cs.wisc.edu l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 9810008Snilay@cs.wisc.edu Icache = l0i_cache, Dcache = l0d_cache, 9910529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 10010300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 10110008Snilay@cs.wisc.edu ruby_system = ruby_system) 10210008Snilay@cs.wisc.edu 10310988Snilay@cs.wisc.edu cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j, 10410988Snilay@cs.wisc.edu icache = l0i_cache, 10510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 10610008Snilay@cs.wisc.edu dcache = l0d_cache, ruby_system = ruby_system) 10710008Snilay@cs.wisc.edu 10810008Snilay@cs.wisc.edu l0_cntrl.sequencer = cpu_seq 10910008Snilay@cs.wisc.edu 11010008Snilay@cs.wisc.edu l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 11110008Snilay@cs.wisc.edu start_index_bit = block_size_bits, is_icache = False) 11210008Snilay@cs.wisc.edu 11310008Snilay@cs.wisc.edu l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 11410008Snilay@cs.wisc.edu cache = l1_cache, l2_select_num_bits = l2_bits, 11510008Snilay@cs.wisc.edu cluster_id = i, ruby_system = ruby_system) 11610008Snilay@cs.wisc.edu 11710008Snilay@cs.wisc.edu exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 11810008Snilay@cs.wisc.edu i*num_cpus_per_cluster+j)) 11910008Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 12010008Snilay@cs.wisc.edu i*num_cpus_per_cluster+j)) 12110008Snilay@cs.wisc.edu 12210008Snilay@cs.wisc.edu # 12310008Snilay@cs.wisc.edu # Add controllers and sequencers to the appropriate lists 12410008Snilay@cs.wisc.edu # 12510008Snilay@cs.wisc.edu cpu_sequencers.append(cpu_seq) 12610008Snilay@cs.wisc.edu l0_cntrl_nodes.append(l0_cntrl) 12710008Snilay@cs.wisc.edu l1_cntrl_nodes.append(l1_cntrl) 12810311Snilay@cs.wisc.edu 12910311Snilay@cs.wisc.edu # Connect the L0 and L1 controllers 13010311Snilay@cs.wisc.edu l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0 13110311Snilay@cs.wisc.edu l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0 13210311Snilay@cs.wisc.edu 13310311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 13410311Snilay@cs.wisc.edu l1_cntrl.requestToL2 = ruby_system.network.slave 13510311Snilay@cs.wisc.edu l1_cntrl.responseToL2 = ruby_system.network.slave 13610311Snilay@cs.wisc.edu l1_cntrl.unblockToL2 = ruby_system.network.slave 13710311Snilay@cs.wisc.edu 13810311Snilay@cs.wisc.edu l1_cntrl.requestFromL2 = ruby_system.network.master 13910311Snilay@cs.wisc.edu l1_cntrl.responseFromL2 = ruby_system.network.master 14010311Snilay@cs.wisc.edu 14110008Snilay@cs.wisc.edu 14210008Snilay@cs.wisc.edu for j in xrange(num_l2caches_per_cluster): 14310008Snilay@cs.wisc.edu l2_cache = L2Cache(size = options.l2_size, 14410008Snilay@cs.wisc.edu assoc = options.l2_assoc, 14510008Snilay@cs.wisc.edu start_index_bit = l2_index_start) 14610008Snilay@cs.wisc.edu 14710008Snilay@cs.wisc.edu l2_cntrl = L2Cache_Controller( 14810008Snilay@cs.wisc.edu version = i * num_l2caches_per_cluster + j, 14910008Snilay@cs.wisc.edu L2cache = l2_cache, cluster_id = i, 15010008Snilay@cs.wisc.edu transitions_per_cycle=options.ports, 15110008Snilay@cs.wisc.edu ruby_system = ruby_system) 15210008Snilay@cs.wisc.edu 15310008Snilay@cs.wisc.edu exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 15410008Snilay@cs.wisc.edu i * num_l2caches_per_cluster + j)) 15510008Snilay@cs.wisc.edu l2_cntrl_nodes.append(l2_cntrl) 15610008Snilay@cs.wisc.edu 15710311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 15810311Snilay@cs.wisc.edu l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave 15910311Snilay@cs.wisc.edu l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave 16010311Snilay@cs.wisc.edu l2_cntrl.responseFromL2Cache = ruby_system.network.slave 16110311Snilay@cs.wisc.edu 16210311Snilay@cs.wisc.edu l2_cntrl.unblockToL2Cache = ruby_system.network.master 16310311Snilay@cs.wisc.edu l2_cntrl.L1RequestToL2Cache = ruby_system.network.master 16410311Snilay@cs.wisc.edu l2_cntrl.responseToL2Cache = ruby_system.network.master 16510311Snilay@cs.wisc.edu 16610008Snilay@cs.wisc.edu phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 16710008Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 16810008Snilay@cs.wisc.edu mem_module_size = phys_mem_size / options.num_dirs 16910008Snilay@cs.wisc.edu 17010008Snilay@cs.wisc.edu # Run each of the ruby memory controllers at a ratio of the frequency of 17110008Snilay@cs.wisc.edu # the ruby system 17210008Snilay@cs.wisc.edu # clk_divider value is a fix to pass regression. 17310008Snilay@cs.wisc.edu ruby_system.memctrl_clk_domain = DerivedClockDomain( 17410008Snilay@cs.wisc.edu clk_domain=ruby_system.clk_domain, 17510008Snilay@cs.wisc.edu clk_divider=3) 17610008Snilay@cs.wisc.edu 17710008Snilay@cs.wisc.edu for i in xrange(options.num_dirs): 17810008Snilay@cs.wisc.edu # 17910008Snilay@cs.wisc.edu # Create the Ruby objects associated with the directory controller 18010008Snilay@cs.wisc.edu # 18110008Snilay@cs.wisc.edu dir_size = MemorySize('0B') 18210008Snilay@cs.wisc.edu dir_size.value = mem_module_size 18310008Snilay@cs.wisc.edu 18410008Snilay@cs.wisc.edu dir_cntrl = Directory_Controller(version = i, 18510524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 18610524Snilay@cs.wisc.edu version = i, size = dir_size), 18710008Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 18810008Snilay@cs.wisc.edu ruby_system = ruby_system) 18910008Snilay@cs.wisc.edu 19010008Snilay@cs.wisc.edu exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 19110008Snilay@cs.wisc.edu dir_cntrl_nodes.append(dir_cntrl) 19210008Snilay@cs.wisc.edu 19310311Snilay@cs.wisc.edu # Connect the directory controllers and the network 19410311Snilay@cs.wisc.edu dir_cntrl.requestToDir = ruby_system.network.master 19510311Snilay@cs.wisc.edu dir_cntrl.responseToDir = ruby_system.network.master 19610311Snilay@cs.wisc.edu dir_cntrl.responseFromDir = ruby_system.network.slave 19710311Snilay@cs.wisc.edu 19810008Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 19910008Snilay@cs.wisc.edu # 20010008Snilay@cs.wisc.edu # Create the Ruby objects associated with the dma controller 20110008Snilay@cs.wisc.edu # 20210008Snilay@cs.wisc.edu dma_seq = DMASequencer(version = i, 20310008Snilay@cs.wisc.edu ruby_system = ruby_system) 20410008Snilay@cs.wisc.edu 20510008Snilay@cs.wisc.edu dma_cntrl = DMA_Controller(version = i, 20610008Snilay@cs.wisc.edu dma_sequencer = dma_seq, 20710008Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 20810008Snilay@cs.wisc.edu ruby_system = ruby_system) 20910008Snilay@cs.wisc.edu 21010008Snilay@cs.wisc.edu exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 21110008Snilay@cs.wisc.edu exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 21210008Snilay@cs.wisc.edu dma_cntrl_nodes.append(dma_cntrl) 21310008Snilay@cs.wisc.edu 21410652Smalek.musleh@gmail.com # Connect the dma controller to the network 21510652Smalek.musleh@gmail.com dma_cntrl.responseFromDir = ruby_system.network.master 21610652Smalek.musleh@gmail.com dma_cntrl.requestToDir = ruby_system.network.slave 21710652Smalek.musleh@gmail.com 21810008Snilay@cs.wisc.edu all_cntrls = l0_cntrl_nodes + \ 21910008Snilay@cs.wisc.edu l1_cntrl_nodes + \ 22010008Snilay@cs.wisc.edu l2_cntrl_nodes + \ 22110008Snilay@cs.wisc.edu dir_cntrl_nodes + \ 22210008Snilay@cs.wisc.edu dma_cntrl_nodes 22310008Snilay@cs.wisc.edu 22410519Snilay@cs.wisc.edu # Create the io controller and the sequencer 22510519Snilay@cs.wisc.edu if full_system: 22610519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 22710519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 22810519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 22910519Snilay@cs.wisc.edu dma_sequencer = io_seq, 23010519Snilay@cs.wisc.edu ruby_system = ruby_system) 23110519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 23210519Snilay@cs.wisc.edu 23310519Snilay@cs.wisc.edu # Connect the dma controller to the network 23410519Snilay@cs.wisc.edu io_controller.responseFromDir = ruby_system.network.master 23510519Snilay@cs.wisc.edu io_controller.requestToDir = ruby_system.network.slave 23610519Snilay@cs.wisc.edu 23710519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 23810519Snilay@cs.wisc.edu 23910008Snilay@cs.wisc.edu topology = create_topology(all_cntrls, options) 24010008Snilay@cs.wisc.edu return (cpu_sequencers, dir_cntrl_nodes, topology) 241