GPU_VIPER.py revision 13731
16899SN/A# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 26899SN/A# All rights reserved. 36899SN/A# 46899SN/A# For use for simulation and test purposes only 56899SN/A# 66899SN/A# Redistribution and use in source and binary forms, with or without 76899SN/A# modification, are permitted provided that the following conditions are met: 86899SN/A# 96899SN/A# 1. Redistributions of source code must retain the above copyright notice, 106899SN/A# this list of conditions and the following disclaimer. 116899SN/A# 126899SN/A# 2. Redistributions in binary form must reproduce the above copyright notice, 136899SN/A# this list of conditions and the following disclaimer in the documentation 146899SN/A# and/or other materials provided with the distribution. 156899SN/A# 166899SN/A# 3. Neither the name of the copyright holder nor the names of its 176899SN/A# contributors may be used to endorse or promote products derived from this 186899SN/A# software without specific prior written permission. 196899SN/A# 206899SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 216899SN/A# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 226899SN/A# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 236899SN/A# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 246899SN/A# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 256899SN/A# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 266899SN/A# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 276899SN/A# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 286899SN/A# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 296899SN/A# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 306899SN/A# POSSIBILITY OF SUCH DAMAGE. 316899SN/A# 326899SN/A# Authors: Lisa Hsu 336899SN/A 346899SN/Aimport math 356899SN/Aimport m5 366899SN/Afrom m5.objects import * 376899SN/Afrom m5.defines import buildEnv 386899SN/Afrom m5.util import addToPath 396899SN/Afrom Ruby import create_topology 406899SN/Afrom Ruby import send_evicts 416899SN/A 426899SN/AaddToPath('../') 436899SN/A 446899SN/Afrom topologies.Cluster import Cluster 456899SN/Afrom topologies.Crossbar import Crossbar 466899SN/A 476899SN/Aclass CntrlBase: 487553SN/A _seqs = 0 497553SN/A @classmethod 506899SN/A def seqCount(cls): 516899SN/A # Use SeqCount not class since we need global count 527553SN/A CntrlBase._seqs += 1 537553SN/A return CntrlBase._seqs - 1 546899SN/A 556899SN/A _cntrls = 0 567538SN/A @classmethod 576899SN/A def cntrlCount(cls): 587538SN/A # Use CntlCount not class since we need global count 596899SN/A CntrlBase._cntrls += 1 606899SN/A return CntrlBase._cntrls - 1 616899SN/A 626899SN/A _version = 0 636899SN/A @classmethod 646899SN/A def versionCount(cls): 656899SN/A cls._version += 1 # Use count for this particular type 666899SN/A return cls._version - 1 676899SN/A 686899SN/Aclass L1Cache(RubyCache): 697632SBrad.Beckmann@amd.com resourceStalls = False 706899SN/A dataArrayBanks = 2 717553SN/A tagArrayBanks = 2 727553SN/A dataAccessLatency = 1 737553SN/A tagAccessLatency = 1 747553SN/A def create(self, size, assoc, options): 757553SN/A self.size = MemorySize(size) 767553SN/A self.assoc = assoc 777553SN/A self.replacement_policy = PseudoLRUReplacementPolicy() 787553SN/A 797553SN/Aclass L2Cache(RubyCache): 807632SBrad.Beckmann@amd.com resourceStalls = False 817553SN/A assoc = 16 826899SN/A dataArrayBanks = 16 836899SN/A tagArrayBanks = 16 846899SN/A def create(self, size, assoc, options): 856899SN/A self.size = MemorySize(size) 866899SN/A self.assoc = assoc 876899SN/A self.replacement_policy = PseudoLRUReplacementPolicy() 886899SN/A 896899SN/Aclass CPCntrl(CorePair_Controller, CntrlBase): 907553SN/A 917553SN/A def create(self, options, ruby_system, system): 927553SN/A self.version = self.versionCount() 937553SN/A 947553SN/A self.L1Icache = L1Cache() 957632SBrad.Beckmann@amd.com self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 967553SN/A self.L1D0cache = L1Cache() 978436SBrad.Beckmann@amd.com self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 986899SN/A self.L1D1cache = L1Cache() 998322Ssteve.reinhardt@amd.com self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 1006899SN/A self.L2cache = L2Cache() 1018322Ssteve.reinhardt@amd.com self.L2cache.create(options.l2_size, options.l2_assoc, options) 1026899SN/A 1036899SN/A self.sequencer = RubySequencer() 1046899SN/A self.sequencer.version = self.seqCount() 1058845Sandreas.hansson@arm.com self.sequencer.icache = self.L1Icache 1066899SN/A self.sequencer.dcache = self.L1D0cache 1076899SN/A self.sequencer.ruby_system = ruby_system 1086899SN/A self.sequencer.coreid = 0 1096899SN/A self.sequencer.is_cpu_sequencer = True 1106899SN/A 1118801Sgblack@eecs.umich.edu self.sequencer1 = RubySequencer() 1126899SN/A self.sequencer1.version = self.seqCount() 1136899SN/A self.sequencer1.icache = self.L1Icache 1146899SN/A self.sequencer1.dcache = self.L1D1cache 1156899SN/A self.sequencer1.ruby_system = ruby_system 1166899SN/A self.sequencer1.coreid = 1 1176899SN/A self.sequencer1.is_cpu_sequencer = True 1187525SN/A 1196899SN/A self.issue_latency = options.cpu_to_dir_latency 1206899SN/A self.send_evictions = send_evicts(options) 1216899SN/A 1226899SN/A self.ruby_system = ruby_system 1236899SN/A 124 if options.recycle_latency: 125 self.recycle_latency = options.recycle_latency 126 127class TCPCache(RubyCache): 128 size = "16kB" 129 assoc = 16 130 dataArrayBanks = 16 #number of data banks 131 tagArrayBanks = 16 #number of tag banks 132 dataAccessLatency = 4 133 tagAccessLatency = 1 134 def create(self, options): 135 self.size = MemorySize(options.tcp_size) 136 self.assoc = options.tcp_assoc 137 self.resourceStalls = options.no_tcc_resource_stalls 138 self.replacement_policy = PseudoLRUReplacementPolicy() 139 140class TCPCntrl(TCP_Controller, CntrlBase): 141 142 def create(self, options, ruby_system, system): 143 self.version = self.versionCount() 144 145 self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency, 146 dataAccessLatency = options.TCP_latency) 147 self.L1cache.resourceStalls = options.no_resource_stalls 148 self.L1cache.create(options) 149 self.issue_latency = 1 150 151 self.coalescer = VIPERCoalescer() 152 self.coalescer.version = self.seqCount() 153 self.coalescer.icache = self.L1cache 154 self.coalescer.dcache = self.L1cache 155 self.coalescer.ruby_system = ruby_system 156 self.coalescer.support_inst_reqs = False 157 self.coalescer.is_cpu_sequencer = False 158 159 self.sequencer = RubySequencer() 160 self.sequencer.version = self.seqCount() 161 self.sequencer.icache = self.L1cache 162 self.sequencer.dcache = self.L1cache 163 self.sequencer.ruby_system = ruby_system 164 self.sequencer.is_cpu_sequencer = True 165 166 self.use_seq_not_coal = False 167 168 self.ruby_system = ruby_system 169 170 if options.recycle_latency: 171 self.recycle_latency = options.recycle_latency 172 173 def createCP(self, options, ruby_system, system): 174 self.version = self.versionCount() 175 176 self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency, 177 dataAccessLatency = options.TCP_latency) 178 self.L1cache.resourceStalls = options.no_resource_stalls 179 self.L1cache.create(options) 180 self.issue_latency = 1 181 182 self.coalescer = VIPERCoalescer() 183 self.coalescer.version = self.seqCount() 184 self.coalescer.icache = self.L1cache 185 self.coalescer.dcache = self.L1cache 186 self.coalescer.ruby_system = ruby_system 187 self.coalescer.support_inst_reqs = False 188 self.coalescer.is_cpu_sequencer = False 189 190 self.sequencer = RubySequencer() 191 self.sequencer.version = self.seqCount() 192 self.sequencer.icache = self.L1cache 193 self.sequencer.dcache = self.L1cache 194 self.sequencer.ruby_system = ruby_system 195 self.sequencer.is_cpu_sequencer = True 196 197 self.use_seq_not_coal = True 198 199 self.ruby_system = ruby_system 200 201 if options.recycle_latency: 202 self.recycle_latency = options.recycle_latency 203 204class SQCCache(RubyCache): 205 dataArrayBanks = 8 206 tagArrayBanks = 8 207 dataAccessLatency = 1 208 tagAccessLatency = 1 209 210 def create(self, options): 211 self.size = MemorySize(options.sqc_size) 212 self.assoc = options.sqc_assoc 213 self.replacement_policy = PseudoLRUReplacementPolicy() 214 215class SQCCntrl(SQC_Controller, CntrlBase): 216 217 def create(self, options, ruby_system, system): 218 self.version = self.versionCount() 219 220 self.L1cache = SQCCache() 221 self.L1cache.create(options) 222 self.L1cache.resourceStalls = options.no_resource_stalls 223 224 self.sequencer = RubySequencer() 225 226 self.sequencer.version = self.seqCount() 227 self.sequencer.icache = self.L1cache 228 self.sequencer.dcache = self.L1cache 229 self.sequencer.ruby_system = ruby_system 230 self.sequencer.support_data_reqs = False 231 self.sequencer.is_cpu_sequencer = False 232 233 self.ruby_system = ruby_system 234 235 if options.recycle_latency: 236 self.recycle_latency = options.recycle_latency 237 238class TCC(RubyCache): 239 size = MemorySize("256kB") 240 assoc = 16 241 dataAccessLatency = 8 242 tagAccessLatency = 2 243 resourceStalls = True 244 def create(self, options): 245 self.assoc = options.tcc_assoc 246 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 247 s = options.num_compute_units 248 tcc_size = s * 128 249 tcc_size = str(tcc_size)+'kB' 250 self.size = MemorySize(tcc_size) 251 self.dataArrayBanks = 64 252 self.tagArrayBanks = 64 253 else: 254 self.size = MemorySize(options.tcc_size) 255 self.dataArrayBanks = 256 / options.num_tccs #number of data banks 256 self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 257 self.size.value = self.size.value / options.num_tccs 258 if ((self.size.value / long(self.assoc)) < 128): 259 self.size.value = long(128 * self.assoc) 260 self.start_index_bit = math.log(options.cacheline_size, 2) + \ 261 math.log(options.num_tccs, 2) 262 self.replacement_policy = PseudoLRUReplacementPolicy() 263 264 265class TCCCntrl(TCC_Controller, CntrlBase): 266 def create(self, options, ruby_system, system): 267 self.version = self.versionCount() 268 self.L2cache = TCC() 269 self.L2cache.create(options) 270 self.L2cache.resourceStalls = options.no_tcc_resource_stalls 271 272 self.ruby_system = ruby_system 273 274 if options.recycle_latency: 275 self.recycle_latency = options.recycle_latency 276 277class L3Cache(RubyCache): 278 dataArrayBanks = 16 279 tagArrayBanks = 16 280 281 def create(self, options, ruby_system, system): 282 self.size = MemorySize(options.l3_size) 283 self.size.value /= options.num_dirs 284 self.assoc = options.l3_assoc 285 self.dataArrayBanks /= options.num_dirs 286 self.tagArrayBanks /= options.num_dirs 287 self.dataArrayBanks /= options.num_dirs 288 self.tagArrayBanks /= options.num_dirs 289 self.dataAccessLatency = options.l3_data_latency 290 self.tagAccessLatency = options.l3_tag_latency 291 self.resourceStalls = False 292 self.replacement_policy = PseudoLRUReplacementPolicy() 293 294class L3Cntrl(L3Cache_Controller, CntrlBase): 295 def create(self, options, ruby_system, system): 296 self.version = self.versionCount() 297 self.L3cache = L3Cache() 298 self.L3cache.create(options, ruby_system, system) 299 300 self.l3_response_latency = max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency) 301 self.ruby_system = ruby_system 302 303 if options.recycle_latency: 304 self.recycle_latency = options.recycle_latency 305 306 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 307 req_to_l3, probe_to_l3, resp_to_l3): 308 self.reqToDir = req_to_dir 309 self.respToDir = resp_to_dir 310 self.l3UnblockToDir = l3_unblock_to_dir 311 self.reqToL3 = req_to_l3 312 self.probeToL3 = probe_to_l3 313 self.respToL3 = resp_to_l3 314 315class DirMem(RubyDirectoryMemory, CntrlBase): 316 def create(self, options, ruby_system, system): 317 self.version = self.versionCount() 318 319 phys_mem_size = AddrRange(options.mem_size).size() 320 mem_module_size = phys_mem_size / options.num_dirs 321 dir_size = MemorySize('0B') 322 dir_size.value = mem_module_size 323 self.size = dir_size 324 325class DirCntrl(Directory_Controller, CntrlBase): 326 def create(self, options, ruby_system, system): 327 self.version = self.versionCount() 328 329 self.response_latency = 30 330 331 self.directory = DirMem() 332 self.directory.create(options, ruby_system, system) 333 334 self.L3CacheMemory = L3Cache() 335 self.L3CacheMemory.create(options, ruby_system, system) 336 337 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 338 self.L3CacheMemory.tagAccessLatency) 339 340 self.number_of_TBEs = options.num_tbes 341 342 self.ruby_system = ruby_system 343 344 if options.recycle_latency: 345 self.recycle_latency = options.recycle_latency 346 347 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 348 req_to_l3, probe_to_l3, resp_to_l3): 349 self.reqToDir = req_to_dir 350 self.respToDir = resp_to_dir 351 self.l3UnblockToDir = l3_unblock_to_dir 352 self.reqToL3 = req_to_l3 353 self.probeToL3 = probe_to_l3 354 self.respToL3 = resp_to_l3 355 356def define_options(parser): 357 parser.add_option("--num-subcaches", type = "int", default = 4) 358 parser.add_option("--l3-data-latency", type = "int", default = 20) 359 parser.add_option("--l3-tag-latency", type = "int", default = 15) 360 parser.add_option("--cpu-to-dir-latency", type = "int", default = 120) 361 parser.add_option("--gpu-to-dir-latency", type = "int", default = 120) 362 parser.add_option("--no-resource-stalls", action = "store_false", 363 default = True) 364 parser.add_option("--no-tcc-resource-stalls", action = "store_false", 365 default = True) 366 parser.add_option("--use-L3-on-WT", action = "store_true", default = False) 367 parser.add_option("--num-tbes", type = "int", default = 256) 368 parser.add_option("--l2-latency", type = "int", default = 50) # load to use 369 parser.add_option("--num-tccs", type = "int", default = 1, 370 help = "number of TCC banks in the GPU") 371 parser.add_option("--sqc-size", type = 'string', default = '32kB', 372 help = "SQC cache size") 373 parser.add_option("--sqc-assoc", type = 'int', default = 8, 374 help = "SQC cache assoc") 375 parser.add_option("--WB_L1", action = "store_true", default = False, 376 help = "writeback L1") 377 parser.add_option("--WB_L2", action = "store_true", default = False, 378 help = "writeback L2") 379 parser.add_option("--TCP_latency", type = "int", default = 4, 380 help = "TCP latency") 381 parser.add_option("--TCC_latency", type = "int", default = 16, 382 help = "TCC latency") 383 parser.add_option("--tcc-size", type = 'string', default = '256kB', 384 help = "agregate tcc size") 385 parser.add_option("--tcc-assoc", type = 'int', default = 16, 386 help = "tcc assoc") 387 parser.add_option("--tcp-size", type = 'string', default = '16kB', 388 help = "tcp size") 389 parser.add_option("--tcp-assoc", type = 'int', default = 16, 390 help = "tcp assoc") 391 parser.add_option("--noL1", action = "store_true", default = False, 392 help = "bypassL1") 393 394def create_system(options, full_system, system, dma_devices, bootmem, 395 ruby_system): 396 if buildEnv['PROTOCOL'] != 'GPU_VIPER': 397 panic("This script requires the GPU_VIPER protocol to be built.") 398 399 cpu_sequencers = [] 400 401 # 402 # The ruby network creation expects the list of nodes in the system to be 403 # consistent with the NetDest list. Therefore the l1 controller nodes 404 # must be listed before the directory nodes and directory nodes before 405 # dma nodes, etc. 406 # 407 cp_cntrl_nodes = [] 408 tcp_cntrl_nodes = [] 409 sqc_cntrl_nodes = [] 410 tcc_cntrl_nodes = [] 411 dir_cntrl_nodes = [] 412 l3_cntrl_nodes = [] 413 414 # 415 # Must create the individual controllers before the network to ensure the 416 # controller constructors are called before the network constructor 417 # 418 419 # For an odd number of CPUs, still create the right number of controllers 420 TCC_bits = int(math.log(options.num_tccs, 2)) 421 422 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 423 # Clusters 424 crossbar_bw = None 425 mainCluster = None 426 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 427 #Assuming a 2GHz clock 428 crossbar_bw = 16 * options.num_compute_units * options.bw_scalor 429 mainCluster = Cluster(intBW=crossbar_bw) 430 else: 431 mainCluster = Cluster(intBW=8) # 16 GB/s 432 for i in range(options.num_dirs): 433 434 dir_cntrl = DirCntrl(noTCCdir = True, TCC_select_num_bits = TCC_bits) 435 dir_cntrl.create(options, ruby_system, system) 436 dir_cntrl.number_of_TBEs = options.num_tbes 437 dir_cntrl.useL3OnWT = options.use_L3_on_WT 438 # the number_of_TBEs is inclusive of TBEs below 439 440 # Connect the Directory controller to the ruby network 441 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 442 dir_cntrl.requestFromCores.slave = ruby_system.network.master 443 444 dir_cntrl.responseFromCores = MessageBuffer() 445 dir_cntrl.responseFromCores.slave = ruby_system.network.master 446 447 dir_cntrl.unblockFromCores = MessageBuffer() 448 dir_cntrl.unblockFromCores.slave = ruby_system.network.master 449 450 dir_cntrl.probeToCore = MessageBuffer() 451 dir_cntrl.probeToCore.master = ruby_system.network.slave 452 453 dir_cntrl.responseToCore = MessageBuffer() 454 dir_cntrl.responseToCore.master = ruby_system.network.slave 455 456 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 457 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 458 dir_cntrl.responseFromMemory = MessageBuffer() 459 460 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 461 dir_cntrl_nodes.append(dir_cntrl) 462 463 mainCluster.add(dir_cntrl) 464 465 cpuCluster = None 466 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 467 cpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) 468 else: 469 cpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s 470 for i in range((options.num_cpus + 1) // 2): 471 472 cp_cntrl = CPCntrl() 473 cp_cntrl.create(options, ruby_system, system) 474 475 exec("ruby_system.cp_cntrl%d = cp_cntrl" % i) 476 # 477 # Add controllers and sequencers to the appropriate lists 478 # 479 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 480 481 # Connect the CP controllers and the network 482 cp_cntrl.requestFromCore = MessageBuffer() 483 cp_cntrl.requestFromCore.master = ruby_system.network.slave 484 485 cp_cntrl.responseFromCore = MessageBuffer() 486 cp_cntrl.responseFromCore.master = ruby_system.network.slave 487 488 cp_cntrl.unblockFromCore = MessageBuffer() 489 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 490 491 cp_cntrl.probeToCore = MessageBuffer() 492 cp_cntrl.probeToCore.slave = ruby_system.network.master 493 494 cp_cntrl.responseToCore = MessageBuffer() 495 cp_cntrl.responseToCore.slave = ruby_system.network.master 496 497 cp_cntrl.mandatoryQueue = MessageBuffer() 498 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 499 500 cpuCluster.add(cp_cntrl) 501 502 gpuCluster = None 503 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 504 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) 505 else: 506 gpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s 507 for i in range(options.num_compute_units): 508 509 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 510 issue_latency = 1, 511 number_of_TBEs = 2560) 512 # TBEs set to max outstanding requests 513 tcp_cntrl.create(options, ruby_system, system) 514 tcp_cntrl.WB = options.WB_L1 515 tcp_cntrl.disableL1 = options.noL1 516 tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency 517 tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency 518 519 exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % i) 520 # 521 # Add controllers and sequencers to the appropriate lists 522 # 523 cpu_sequencers.append(tcp_cntrl.coalescer) 524 tcp_cntrl_nodes.append(tcp_cntrl) 525 526 # Connect the TCP controller to the ruby network 527 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 528 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 529 530 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 531 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 532 533 tcp_cntrl.unblockFromCore = MessageBuffer() 534 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 535 536 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 537 tcp_cntrl.probeToTCP.slave = ruby_system.network.master 538 539 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 540 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 541 542 tcp_cntrl.mandatoryQueue = MessageBuffer() 543 544 gpuCluster.add(tcp_cntrl) 545 546 for i in range(options.num_sqc): 547 548 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 549 sqc_cntrl.create(options, ruby_system, system) 550 551 exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % i) 552 # 553 # Add controllers and sequencers to the appropriate lists 554 # 555 cpu_sequencers.append(sqc_cntrl.sequencer) 556 557 # Connect the SQC controller to the ruby network 558 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 559 sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 560 561 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 562 sqc_cntrl.probeToSQC.slave = ruby_system.network.master 563 564 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 565 sqc_cntrl.responseToSQC.slave = ruby_system.network.master 566 567 sqc_cntrl.mandatoryQueue = MessageBuffer() 568 569 # SQC also in GPU cluster 570 gpuCluster.add(sqc_cntrl) 571 572 for i in range(options.num_cp): 573 574 tcp_ID = options.num_compute_units + i 575 sqc_ID = options.num_sqc + i 576 577 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 578 issue_latency = 1, 579 number_of_TBEs = 2560) 580 # TBEs set to max outstanding requests 581 tcp_cntrl.createCP(options, ruby_system, system) 582 tcp_cntrl.WB = options.WB_L1 583 tcp_cntrl.disableL1 = options.noL1 584 tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency 585 tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency 586 587 exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % tcp_ID) 588 # 589 # Add controllers and sequencers to the appropriate lists 590 # 591 cpu_sequencers.append(tcp_cntrl.sequencer) 592 tcp_cntrl_nodes.append(tcp_cntrl) 593 594 # Connect the CP (TCP) controllers to the ruby network 595 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 596 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 597 598 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 599 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 600 601 tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True) 602 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 603 604 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 605 tcp_cntrl.probeToTCP.slave = ruby_system.network.master 606 607 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 608 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 609 610 tcp_cntrl.mandatoryQueue = MessageBuffer() 611 612 gpuCluster.add(tcp_cntrl) 613 614 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 615 sqc_cntrl.create(options, ruby_system, system) 616 617 exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % sqc_ID) 618 # 619 # Add controllers and sequencers to the appropriate lists 620 # 621 cpu_sequencers.append(sqc_cntrl.sequencer) 622 623 # SQC also in GPU cluster 624 gpuCluster.add(sqc_cntrl) 625 626 for i in range(options.num_tccs): 627 628 tcc_cntrl = TCCCntrl(l2_response_latency = options.TCC_latency) 629 tcc_cntrl.create(options, ruby_system, system) 630 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 631 tcc_cntrl.l2_response_latency = options.TCC_latency 632 tcc_cntrl_nodes.append(tcc_cntrl) 633 tcc_cntrl.WB = options.WB_L2 634 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units 635 # the number_of_TBEs is inclusive of TBEs below 636 637 # Connect the TCC controllers to the ruby network 638 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True) 639 tcc_cntrl.requestFromTCP.slave = ruby_system.network.master 640 641 tcc_cntrl.responseToCore = MessageBuffer(ordered = True) 642 tcc_cntrl.responseToCore.master = ruby_system.network.slave 643 644 tcc_cntrl.probeFromNB = MessageBuffer() 645 tcc_cntrl.probeFromNB.slave = ruby_system.network.master 646 647 tcc_cntrl.responseFromNB = MessageBuffer() 648 tcc_cntrl.responseFromNB.slave = ruby_system.network.master 649 650 tcc_cntrl.requestToNB = MessageBuffer(ordered = True) 651 tcc_cntrl.requestToNB.master = ruby_system.network.slave 652 653 tcc_cntrl.responseToNB = MessageBuffer() 654 tcc_cntrl.responseToNB.master = ruby_system.network.slave 655 656 tcc_cntrl.unblockToNB = MessageBuffer() 657 tcc_cntrl.unblockToNB.master = ruby_system.network.slave 658 659 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True) 660 661 exec("ruby_system.tcc_cntrl%d = tcc_cntrl" % i) 662 663 # connect all of the wire buffers between L3 and dirs up 664 # TCC cntrls added to the GPU cluster 665 gpuCluster.add(tcc_cntrl) 666 667 # Assuming no DMA devices 668 assert(len(dma_devices) == 0) 669 670 # Add cpu/gpu clusters to main cluster 671 mainCluster.add(cpuCluster) 672 mainCluster.add(gpuCluster) 673 674 ruby_system.network.number_of_virtual_networks = 10 675 676 return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 677