GPU_VIPER.py revision 12598:b80b2d9a251b
17322Sgblack@eecs.umich.edu# 27322Sgblack@eecs.umich.edu# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 310037SARM gem5 Developers# All rights reserved. 47322Sgblack@eecs.umich.edu# 57322Sgblack@eecs.umich.edu# For use for simulation and test purposes only 67322Sgblack@eecs.umich.edu# 77322Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 87322Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are met: 97322Sgblack@eecs.umich.edu# 107322Sgblack@eecs.umich.edu# 1. Redistributions of source code must retain the above copyright notice, 117322Sgblack@eecs.umich.edu# this list of conditions and the following disclaimer. 127322Sgblack@eecs.umich.edu# 137322Sgblack@eecs.umich.edu# 2. Redistributions in binary form must reproduce the above copyright notice, 147322Sgblack@eecs.umich.edu# this list of conditions and the following disclaimer in the documentation 157322Sgblack@eecs.umich.edu# and/or other materials provided with the distribution. 167322Sgblack@eecs.umich.edu# 177322Sgblack@eecs.umich.edu# 3. Neither the name of the copyright holder nor the names of its contributors 187322Sgblack@eecs.umich.edu# may be used to endorse or promote products derived from this software 197322Sgblack@eecs.umich.edu# without specific prior written permission. 207322Sgblack@eecs.umich.edu# 217322Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 227322Sgblack@eecs.umich.edu# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 237322Sgblack@eecs.umich.edu# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 247322Sgblack@eecs.umich.edu# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 257322Sgblack@eecs.umich.edu# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 267322Sgblack@eecs.umich.edu# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 277322Sgblack@eecs.umich.edu# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 287322Sgblack@eecs.umich.edu# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 297322Sgblack@eecs.umich.edu# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 307322Sgblack@eecs.umich.edu# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 317322Sgblack@eecs.umich.edu# POSSIBILITY OF SUCH DAMAGE. 327322Sgblack@eecs.umich.edu# 337322Sgblack@eecs.umich.edu# Author: Lisa Hsu 347322Sgblack@eecs.umich.edu# 357322Sgblack@eecs.umich.edu 367322Sgblack@eecs.umich.eduimport math 377322Sgblack@eecs.umich.eduimport m5 387322Sgblack@eecs.umich.edufrom m5.objects import * 397322Sgblack@eecs.umich.edufrom m5.defines import buildEnv 407376Sgblack@eecs.umich.edufrom Ruby import create_topology 417376Sgblack@eecs.umich.edufrom Ruby import send_evicts 427376Sgblack@eecs.umich.edu 437376Sgblack@eecs.umich.edufrom topologies.Cluster import Cluster 447376Sgblack@eecs.umich.edufrom topologies.Crossbar import Crossbar 457376Sgblack@eecs.umich.edu 467376Sgblack@eecs.umich.educlass CntrlBase: 477376Sgblack@eecs.umich.edu _seqs = 0 487376Sgblack@eecs.umich.edu @classmethod 497376Sgblack@eecs.umich.edu def seqCount(cls): 507376Sgblack@eecs.umich.edu # Use SeqCount not class since we need global count 517376Sgblack@eecs.umich.edu CntrlBase._seqs += 1 527376Sgblack@eecs.umich.edu return CntrlBase._seqs - 1 537376Sgblack@eecs.umich.edu 547376Sgblack@eecs.umich.edu _cntrls = 0 557376Sgblack@eecs.umich.edu @classmethod 567376Sgblack@eecs.umich.edu def cntrlCount(cls): 577376Sgblack@eecs.umich.edu # Use CntlCount not class since we need global count 587376Sgblack@eecs.umich.edu CntrlBase._cntrls += 1 597376Sgblack@eecs.umich.edu return CntrlBase._cntrls - 1 607376Sgblack@eecs.umich.edu 617376Sgblack@eecs.umich.edu _version = 0 627376Sgblack@eecs.umich.edu @classmethod 637376Sgblack@eecs.umich.edu def versionCount(cls): 647376Sgblack@eecs.umich.edu cls._version += 1 # Use count for this particular type 657376Sgblack@eecs.umich.edu return cls._version - 1 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.educlass L1Cache(RubyCache): 687376Sgblack@eecs.umich.edu resourceStalls = False 697376Sgblack@eecs.umich.edu dataArrayBanks = 2 707376Sgblack@eecs.umich.edu tagArrayBanks = 2 717376Sgblack@eecs.umich.edu dataAccessLatency = 1 727376Sgblack@eecs.umich.edu tagAccessLatency = 1 737376Sgblack@eecs.umich.edu def create(self, size, assoc, options): 747376Sgblack@eecs.umich.edu self.size = MemorySize(size) 757376Sgblack@eecs.umich.edu self.assoc = assoc 767376Sgblack@eecs.umich.edu self.replacement_policy = PseudoLRUReplacementPolicy() 777376Sgblack@eecs.umich.edu 787376Sgblack@eecs.umich.educlass L2Cache(RubyCache): 797376Sgblack@eecs.umich.edu resourceStalls = False 807376Sgblack@eecs.umich.edu assoc = 16 817376Sgblack@eecs.umich.edu dataArrayBanks = 16 827376Sgblack@eecs.umich.edu tagArrayBanks = 16 837376Sgblack@eecs.umich.edu def create(self, size, assoc, options): 847376Sgblack@eecs.umich.edu self.size = MemorySize(size) 857376Sgblack@eecs.umich.edu self.assoc = assoc 867376Sgblack@eecs.umich.edu self.replacement_policy = PseudoLRUReplacementPolicy() 877376Sgblack@eecs.umich.edu 887376Sgblack@eecs.umich.educlass CPCntrl(CorePair_Controller, CntrlBase): 897376Sgblack@eecs.umich.edu 907376Sgblack@eecs.umich.edu def create(self, options, ruby_system, system): 917376Sgblack@eecs.umich.edu self.version = self.versionCount() 927376Sgblack@eecs.umich.edu 937376Sgblack@eecs.umich.edu self.L1Icache = L1Cache() 947376Sgblack@eecs.umich.edu self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 957376Sgblack@eecs.umich.edu self.L1D0cache = L1Cache() 967376Sgblack@eecs.umich.edu self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 977376Sgblack@eecs.umich.edu self.L1D1cache = L1Cache() 987376Sgblack@eecs.umich.edu self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 997376Sgblack@eecs.umich.edu self.L2cache = L2Cache() 1007376Sgblack@eecs.umich.edu self.L2cache.create(options.l2_size, options.l2_assoc, options) 1017376Sgblack@eecs.umich.edu 1027376Sgblack@eecs.umich.edu self.sequencer = RubySequencer() 1037376Sgblack@eecs.umich.edu self.sequencer.version = self.seqCount() 1047376Sgblack@eecs.umich.edu self.sequencer.icache = self.L1Icache 1057376Sgblack@eecs.umich.edu self.sequencer.dcache = self.L1D0cache 1067376Sgblack@eecs.umich.edu self.sequencer.ruby_system = ruby_system 1077376Sgblack@eecs.umich.edu self.sequencer.coreid = 0 1087376Sgblack@eecs.umich.edu self.sequencer.is_cpu_sequencer = True 1097376Sgblack@eecs.umich.edu 1107376Sgblack@eecs.umich.edu self.sequencer1 = RubySequencer() 1117376Sgblack@eecs.umich.edu self.sequencer1.version = self.seqCount() 1127376Sgblack@eecs.umich.edu self.sequencer1.icache = self.L1Icache 1137376Sgblack@eecs.umich.edu self.sequencer1.dcache = self.L1D1cache 1147376Sgblack@eecs.umich.edu self.sequencer1.ruby_system = ruby_system 1157376Sgblack@eecs.umich.edu self.sequencer1.coreid = 1 1167376Sgblack@eecs.umich.edu self.sequencer1.is_cpu_sequencer = True 1177376Sgblack@eecs.umich.edu 1187376Sgblack@eecs.umich.edu self.issue_latency = options.cpu_to_dir_latency 1197376Sgblack@eecs.umich.edu self.send_evictions = send_evicts(options) 1207376Sgblack@eecs.umich.edu 1217376Sgblack@eecs.umich.edu self.ruby_system = ruby_system 1227376Sgblack@eecs.umich.edu 1237376Sgblack@eecs.umich.edu if options.recycle_latency: 1247376Sgblack@eecs.umich.edu self.recycle_latency = options.recycle_latency 1257376Sgblack@eecs.umich.edu 1267376Sgblack@eecs.umich.educlass TCPCache(RubyCache): 1277376Sgblack@eecs.umich.edu size = "16kB" 1287376Sgblack@eecs.umich.edu assoc = 16 1297376Sgblack@eecs.umich.edu dataArrayBanks = 16 #number of data banks 1307376Sgblack@eecs.umich.edu tagArrayBanks = 16 #number of tag banks 1317376Sgblack@eecs.umich.edu dataAccessLatency = 4 1327376Sgblack@eecs.umich.edu tagAccessLatency = 1 1337376Sgblack@eecs.umich.edu def create(self, options): 1347376Sgblack@eecs.umich.edu self.size = MemorySize(options.tcp_size) 1357376Sgblack@eecs.umich.edu self.assoc = options.tcp_assoc 1367376Sgblack@eecs.umich.edu self.resourceStalls = options.no_tcc_resource_stalls 1377376Sgblack@eecs.umich.edu self.replacement_policy = PseudoLRUReplacementPolicy() 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.educlass TCPCntrl(TCP_Controller, CntrlBase): 1407376Sgblack@eecs.umich.edu 1417376Sgblack@eecs.umich.edu def create(self, options, ruby_system, system): 1427376Sgblack@eecs.umich.edu self.version = self.versionCount() 1437376Sgblack@eecs.umich.edu 1447376Sgblack@eecs.umich.edu self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency, 1457376Sgblack@eecs.umich.edu dataAccessLatency = options.TCP_latency) 1467376Sgblack@eecs.umich.edu self.L1cache.resourceStalls = options.no_resource_stalls 1477376Sgblack@eecs.umich.edu self.L1cache.create(options) 1487376Sgblack@eecs.umich.edu self.issue_latency = 1 1497376Sgblack@eecs.umich.edu 1507376Sgblack@eecs.umich.edu self.coalescer = VIPERCoalescer() 1517376Sgblack@eecs.umich.edu self.coalescer.version = self.seqCount() 1527376Sgblack@eecs.umich.edu self.coalescer.icache = self.L1cache 1537376Sgblack@eecs.umich.edu self.coalescer.dcache = self.L1cache 1547376Sgblack@eecs.umich.edu self.coalescer.ruby_system = ruby_system 1557376Sgblack@eecs.umich.edu self.coalescer.support_inst_reqs = False 1567376Sgblack@eecs.umich.edu self.coalescer.is_cpu_sequencer = False 1577376Sgblack@eecs.umich.edu 1587376Sgblack@eecs.umich.edu self.sequencer = RubySequencer() 1597376Sgblack@eecs.umich.edu self.sequencer.version = self.seqCount() 1607376Sgblack@eecs.umich.edu self.sequencer.icache = self.L1cache 1617376Sgblack@eecs.umich.edu self.sequencer.dcache = self.L1cache 1627376Sgblack@eecs.umich.edu self.sequencer.ruby_system = ruby_system 1637376Sgblack@eecs.umich.edu self.sequencer.is_cpu_sequencer = True 1647376Sgblack@eecs.umich.edu 1657376Sgblack@eecs.umich.edu self.use_seq_not_coal = False 1667376Sgblack@eecs.umich.edu 1677376Sgblack@eecs.umich.edu self.ruby_system = ruby_system 1687376Sgblack@eecs.umich.edu 1697376Sgblack@eecs.umich.edu if options.recycle_latency: 1707376Sgblack@eecs.umich.edu self.recycle_latency = options.recycle_latency 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu def createCP(self, options, ruby_system, system): 1737376Sgblack@eecs.umich.edu self.version = self.versionCount() 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edu self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency, 1767376Sgblack@eecs.umich.edu dataAccessLatency = options.TCP_latency) 1777376Sgblack@eecs.umich.edu self.L1cache.resourceStalls = options.no_resource_stalls 1787376Sgblack@eecs.umich.edu self.L1cache.create(options) 1797376Sgblack@eecs.umich.edu self.issue_latency = 1 1807376Sgblack@eecs.umich.edu 1817376Sgblack@eecs.umich.edu self.coalescer = VIPERCoalescer() 1827376Sgblack@eecs.umich.edu self.coalescer.version = self.seqCount() 1837376Sgblack@eecs.umich.edu self.coalescer.icache = self.L1cache 1847376Sgblack@eecs.umich.edu self.coalescer.dcache = self.L1cache 1857376Sgblack@eecs.umich.edu self.coalescer.ruby_system = ruby_system 1867376Sgblack@eecs.umich.edu self.coalescer.support_inst_reqs = False 1877376Sgblack@eecs.umich.edu self.coalescer.is_cpu_sequencer = False 1887322Sgblack@eecs.umich.edu 1897322Sgblack@eecs.umich.edu self.sequencer = RubySequencer() 1907322Sgblack@eecs.umich.edu self.sequencer.version = self.seqCount() 1917322Sgblack@eecs.umich.edu self.sequencer.icache = self.L1cache 1927322Sgblack@eecs.umich.edu self.sequencer.dcache = self.L1cache 1937322Sgblack@eecs.umich.edu self.sequencer.ruby_system = ruby_system 19410037SARM gem5 Developers self.sequencer.is_cpu_sequencer = True 19510037SARM gem5 Developers 19610037SARM gem5 Developers self.use_seq_not_coal = True 19710037SARM gem5 Developers 19810037SARM gem5 Developers self.ruby_system = ruby_system 19910037SARM gem5 Developers 2007760SGiacomo.Gabrielli@arm.com if options.recycle_latency: 2017760SGiacomo.Gabrielli@arm.com self.recycle_latency = options.recycle_latency 2027648SAli.Saidi@ARM.com 20310037SARM gem5 Developersclass SQCCache(RubyCache): 20410037SARM gem5 Developers dataArrayBanks = 8 2057322Sgblack@eecs.umich.edu tagArrayBanks = 8 2067324Sgblack@eecs.umich.edu dataAccessLatency = 1 2077644Sali.saidi@arm.com tagAccessLatency = 1 2087643Sgblack@eecs.umich.edu 2097643Sgblack@eecs.umich.edu def create(self, options): 2107643Sgblack@eecs.umich.edu self.size = MemorySize(options.sqc_size) 2117643Sgblack@eecs.umich.edu self.assoc = options.sqc_assoc 2127643Sgblack@eecs.umich.edu self.replacement_policy = PseudoLRUReplacementPolicy() 2137760SGiacomo.Gabrielli@arm.com 2147783SGiacomo.Gabrielli@arm.comclass SQCCntrl(SQC_Controller, CntrlBase): 2158070SAli.Saidi@ARM.com 2168070SAli.Saidi@ARM.com def create(self, options, ruby_system, system): 2177643Sgblack@eecs.umich.edu self.version = self.versionCount() 2187643Sgblack@eecs.umich.edu 2197643Sgblack@eecs.umich.edu self.L1cache = SQCCache() 2207643Sgblack@eecs.umich.edu self.L1cache.create(options) 22110037SARM gem5 Developers self.L1cache.resourceStalls = options.no_resource_stalls 22210037SARM gem5 Developers 22310037SARM gem5 Developers self.sequencer = RubySequencer() 22410037SARM gem5 Developers 22510037SARM gem5 Developers self.sequencer.version = self.seqCount() 22610037SARM gem5 Developers self.sequencer.icache = self.L1cache 22710037SARM gem5 Developers self.sequencer.dcache = self.L1cache 22810037SARM gem5 Developers self.sequencer.ruby_system = ruby_system 22910037SARM gem5 Developers self.sequencer.support_data_reqs = False 23010037SARM gem5 Developers self.sequencer.is_cpu_sequencer = False 23110037SARM gem5 Developers 23210037SARM gem5 Developers self.ruby_system = ruby_system 23310037SARM gem5 Developers 23410037SARM gem5 Developers if options.recycle_latency: 23510037SARM gem5 Developers self.recycle_latency = options.recycle_latency 23610037SARM gem5 Developers 23710474Sandreas.hansson@arm.comclass TCC(RubyCache): 23810037SARM gem5 Developers size = MemorySize("256kB") 23910037SARM gem5 Developers assoc = 16 24010037SARM gem5 Developers dataAccessLatency = 8 24110037SARM gem5 Developers tagAccessLatency = 2 24210037SARM gem5 Developers resourceStalls = True 24310037SARM gem5 Developers def create(self, options): 24410037SARM gem5 Developers self.assoc = options.tcc_assoc 24510037SARM gem5 Developers if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 2467760SGiacomo.Gabrielli@arm.com s = options.num_compute_units 2477783SGiacomo.Gabrielli@arm.com tcc_size = s * 128 2487783SGiacomo.Gabrielli@arm.com tcc_size = str(tcc_size)+'kB' 24910037SARM gem5 Developers self.size = MemorySize(tcc_size) 25010037SARM gem5 Developers self.dataArrayBanks = 64 2517324Sgblack@eecs.umich.edu self.tagArrayBanks = 64 2527333Sgblack@eecs.umich.edu else: 2537643Sgblack@eecs.umich.edu self.size = MemorySize(options.tcc_size) 2547644Sali.saidi@arm.com self.dataArrayBanks = 256 / options.num_tccs #number of data banks 2557643Sgblack@eecs.umich.edu self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 2567760SGiacomo.Gabrielli@arm.com self.size.value = self.size.value / options.num_tccs 2577783SGiacomo.Gabrielli@arm.com if ((self.size.value / long(self.assoc)) < 128): 2587783SGiacomo.Gabrielli@arm.com self.size.value = long(128 * self.assoc) 2597643Sgblack@eecs.umich.edu self.start_index_bit = math.log(options.cacheline_size, 2) + \ 2607643Sgblack@eecs.umich.edu math.log(options.num_tccs, 2) 2617643Sgblack@eecs.umich.edu self.replacement_policy = PseudoLRUReplacementPolicy() 2627643Sgblack@eecs.umich.edu 2638303SAli.Saidi@ARM.com 2648303SAli.Saidi@ARM.comclass TCCCntrl(TCC_Controller, CntrlBase): 2658303SAli.Saidi@ARM.com def create(self, options, ruby_system, system): 2668303SAli.Saidi@ARM.com self.version = self.versionCount() 2678303SAli.Saidi@ARM.com self.L2cache = TCC() 2687643Sgblack@eecs.umich.edu self.L2cache.create(options) 2698303SAli.Saidi@ARM.com self.L2cache.resourceStalls = options.no_tcc_resource_stalls 2707643Sgblack@eecs.umich.edu 2717760SGiacomo.Gabrielli@arm.com self.ruby_system = ruby_system 2728303SAli.Saidi@ARM.com 2738303SAli.Saidi@ARM.com if options.recycle_latency: 2748303SAli.Saidi@ARM.com self.recycle_latency = options.recycle_latency 2757643Sgblack@eecs.umich.edu 2767643Sgblack@eecs.umich.educlass L3Cache(RubyCache): 2777640Sgblack@eecs.umich.edu dataArrayBanks = 16 2788588Sgblack@eecs.umich.edu tagArrayBanks = 16 2797333Sgblack@eecs.umich.edu 2807396Sgblack@eecs.umich.edu def create(self, options, ruby_system, system): 2817333Sgblack@eecs.umich.edu self.size = MemorySize(options.l3_size) 2827760SGiacomo.Gabrielli@arm.com self.size.value /= options.num_dirs 2837760SGiacomo.Gabrielli@arm.com self.assoc = options.l3_assoc 2847396Sgblack@eecs.umich.edu self.dataArrayBanks /= options.num_dirs 2857396Sgblack@eecs.umich.edu self.tagArrayBanks /= options.num_dirs 2867333Sgblack@eecs.umich.edu self.dataArrayBanks /= options.num_dirs 2877333Sgblack@eecs.umich.edu self.tagArrayBanks /= options.num_dirs 2887640Sgblack@eecs.umich.edu self.dataAccessLatency = options.l3_data_latency 2898588Sgblack@eecs.umich.edu self.tagAccessLatency = options.l3_tag_latency 2908588Sgblack@eecs.umich.edu self.resourceStalls = False 2917333Sgblack@eecs.umich.edu self.replacement_policy = PseudoLRUReplacementPolicy() 2927396Sgblack@eecs.umich.edu 2937333Sgblack@eecs.umich.educlass L3Cntrl(L3Cache_Controller, CntrlBase): 2947760SGiacomo.Gabrielli@arm.com def create(self, options, ruby_system, system): 2957760SGiacomo.Gabrielli@arm.com self.version = self.versionCount() 2967396Sgblack@eecs.umich.edu self.L3cache = L3Cache() 2977396Sgblack@eecs.umich.edu self.L3cache.create(options, ruby_system, system) 2987333Sgblack@eecs.umich.edu 2997333Sgblack@eecs.umich.edu self.l3_response_latency = max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency) 3007640Sgblack@eecs.umich.edu self.ruby_system = ruby_system 3018588Sgblack@eecs.umich.edu 3028588Sgblack@eecs.umich.edu if options.recycle_latency: 3038588Sgblack@eecs.umich.edu self.recycle_latency = options.recycle_latency 3048588Sgblack@eecs.umich.edu 3057333Sgblack@eecs.umich.edu def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 3067396Sgblack@eecs.umich.edu req_to_l3, probe_to_l3, resp_to_l3): 3077333Sgblack@eecs.umich.edu self.reqToDir = req_to_dir 3087760SGiacomo.Gabrielli@arm.com self.respToDir = resp_to_dir 3097760SGiacomo.Gabrielli@arm.com self.l3UnblockToDir = l3_unblock_to_dir 3107396Sgblack@eecs.umich.edu self.reqToL3 = req_to_l3 3117396Sgblack@eecs.umich.edu self.probeToL3 = probe_to_l3 3127333Sgblack@eecs.umich.edu self.respToL3 = resp_to_l3 3137333Sgblack@eecs.umich.edu 3147640Sgblack@eecs.umich.educlass DirMem(RubyDirectoryMemory, CntrlBase): 3158588Sgblack@eecs.umich.edu def create(self, options, ruby_system, system): 3167333Sgblack@eecs.umich.edu self.version = self.versionCount() 3177396Sgblack@eecs.umich.edu 3187333Sgblack@eecs.umich.edu phys_mem_size = AddrRange(options.mem_size).size() 3197760SGiacomo.Gabrielli@arm.com mem_module_size = phys_mem_size / options.num_dirs 3207760SGiacomo.Gabrielli@arm.com dir_size = MemorySize('0B') 3217396Sgblack@eecs.umich.edu dir_size.value = mem_module_size 3227396Sgblack@eecs.umich.edu self.size = dir_size 3237333Sgblack@eecs.umich.edu 3247333Sgblack@eecs.umich.educlass DirCntrl(Directory_Controller, CntrlBase): 3257640Sgblack@eecs.umich.edu def create(self, options, ruby_system, system): 3268588Sgblack@eecs.umich.edu self.version = self.versionCount() 3278588Sgblack@eecs.umich.edu 3287333Sgblack@eecs.umich.edu self.response_latency = 30 3297396Sgblack@eecs.umich.edu 3307333Sgblack@eecs.umich.edu self.directory = DirMem() 3317760SGiacomo.Gabrielli@arm.com self.directory.create(options, ruby_system, system) 3327760SGiacomo.Gabrielli@arm.com 3337396Sgblack@eecs.umich.edu self.L3CacheMemory = L3Cache() 3347396Sgblack@eecs.umich.edu self.L3CacheMemory.create(options, ruby_system, system) 3357333Sgblack@eecs.umich.edu 3367333Sgblack@eecs.umich.edu self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 3377640Sgblack@eecs.umich.edu self.L3CacheMemory.tagAccessLatency) 3388588Sgblack@eecs.umich.edu 3398588Sgblack@eecs.umich.edu self.number_of_TBEs = options.num_tbes 3408588Sgblack@eecs.umich.edu 3418588Sgblack@eecs.umich.edu self.ruby_system = ruby_system 3427333Sgblack@eecs.umich.edu 3437396Sgblack@eecs.umich.edu if options.recycle_latency: 3447333Sgblack@eecs.umich.edu self.recycle_latency = options.recycle_latency 3457760SGiacomo.Gabrielli@arm.com 3467760SGiacomo.Gabrielli@arm.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 3477396Sgblack@eecs.umich.edu req_to_l3, probe_to_l3, resp_to_l3): 3487396Sgblack@eecs.umich.edu self.reqToDir = req_to_dir 3497333Sgblack@eecs.umich.edu self.respToDir = resp_to_dir 3507333Sgblack@eecs.umich.edu self.l3UnblockToDir = l3_unblock_to_dir 35110037SARM gem5 Developers self.reqToL3 = req_to_l3 3528588Sgblack@eecs.umich.edu self.probeToL3 = probe_to_l3 3537333Sgblack@eecs.umich.edu self.respToL3 = resp_to_l3 3547396Sgblack@eecs.umich.edu 3557333Sgblack@eecs.umich.edudef define_options(parser): 3567760SGiacomo.Gabrielli@arm.com parser.add_option("--num-subcaches", type = "int", default = 4) 3577760SGiacomo.Gabrielli@arm.com parser.add_option("--l3-data-latency", type = "int", default = 20) 3587396Sgblack@eecs.umich.edu parser.add_option("--l3-tag-latency", type = "int", default = 15) 3597396Sgblack@eecs.umich.edu parser.add_option("--cpu-to-dir-latency", type = "int", default = 120) 3607333Sgblack@eecs.umich.edu parser.add_option("--gpu-to-dir-latency", type = "int", default = 120) 3617333Sgblack@eecs.umich.edu parser.add_option("--no-resource-stalls", action = "store_false", 36210037SARM gem5 Developers default = True) 3638588Sgblack@eecs.umich.edu parser.add_option("--no-tcc-resource-stalls", action = "store_false", 3647333Sgblack@eecs.umich.edu default = True) 3657396Sgblack@eecs.umich.edu parser.add_option("--use-L3-on-WT", action = "store_true", default = False) 3667333Sgblack@eecs.umich.edu parser.add_option("--num-tbes", type = "int", default = 256) 3677760SGiacomo.Gabrielli@arm.com parser.add_option("--l2-latency", type = "int", default = 50) # load to use 3687760SGiacomo.Gabrielli@arm.com parser.add_option("--num-tccs", type = "int", default = 1, 3697396Sgblack@eecs.umich.edu help = "number of TCC banks in the GPU") 3707396Sgblack@eecs.umich.edu parser.add_option("--sqc-size", type = 'string', default = '32kB', 3717333Sgblack@eecs.umich.edu help = "SQC cache size") 3727333Sgblack@eecs.umich.edu parser.add_option("--sqc-assoc", type = 'int', default = 8, 3737640Sgblack@eecs.umich.edu help = "SQC cache assoc") 3748588Sgblack@eecs.umich.edu parser.add_option("--WB_L1", action = "store_true", default = False, 3757333Sgblack@eecs.umich.edu help = "writeback L1") 3767396Sgblack@eecs.umich.edu parser.add_option("--WB_L2", action = "store_true", default = False, 3777333Sgblack@eecs.umich.edu help = "writeback L2") 3787760SGiacomo.Gabrielli@arm.com parser.add_option("--TCP_latency", type = "int", default = 4, 3797760SGiacomo.Gabrielli@arm.com help = "TCP latency") 3807396Sgblack@eecs.umich.edu parser.add_option("--TCC_latency", type = "int", default = 16, 3817396Sgblack@eecs.umich.edu help = "TCC latency") 3827333Sgblack@eecs.umich.edu parser.add_option("--tcc-size", type = 'string', default = '256kB', 3837333Sgblack@eecs.umich.edu help = "agregate tcc size") 3847640Sgblack@eecs.umich.edu parser.add_option("--tcc-assoc", type = 'int', default = 16, 3857639Sgblack@eecs.umich.edu help = "tcc assoc") 3868588Sgblack@eecs.umich.edu parser.add_option("--tcp-size", type = 'string', default = '16kB', 3877333Sgblack@eecs.umich.edu help = "tcp size") 3887396Sgblack@eecs.umich.edu parser.add_option("--tcp-assoc", type = 'int', default = 16, 3897333Sgblack@eecs.umich.edu help = "tcp assoc") 3907760SGiacomo.Gabrielli@arm.com parser.add_option("--noL1", action = "store_true", default = False, 3917760SGiacomo.Gabrielli@arm.com help = "bypassL1") 3927396Sgblack@eecs.umich.edu 3937396Sgblack@eecs.umich.edudef create_system(options, full_system, system, dma_devices, bootmem, 3947333Sgblack@eecs.umich.edu ruby_system): 3957333Sgblack@eecs.umich.edu if buildEnv['PROTOCOL'] != 'GPU_VIPER': 3967640Sgblack@eecs.umich.edu panic("This script requires the GPU_VIPER protocol to be built.") 3977639Sgblack@eecs.umich.edu 3988588Sgblack@eecs.umich.edu cpu_sequencers = [] 3997333Sgblack@eecs.umich.edu 4007396Sgblack@eecs.umich.edu # 4017333Sgblack@eecs.umich.edu # The ruby network creation expects the list of nodes in the system to be 4027760SGiacomo.Gabrielli@arm.com # consistent with the NetDest list. Therefore the l1 controller nodes 4037760SGiacomo.Gabrielli@arm.com # must be listed before the directory nodes and directory nodes before 4047396Sgblack@eecs.umich.edu # dma nodes, etc. 4057396Sgblack@eecs.umich.edu # 4067333Sgblack@eecs.umich.edu cp_cntrl_nodes = [] 4077333Sgblack@eecs.umich.edu tcp_cntrl_nodes = [] 4087640Sgblack@eecs.umich.edu sqc_cntrl_nodes = [] 4097639Sgblack@eecs.umich.edu tcc_cntrl_nodes = [] 4108588Sgblack@eecs.umich.edu dir_cntrl_nodes = [] 4117333Sgblack@eecs.umich.edu l3_cntrl_nodes = [] 4127396Sgblack@eecs.umich.edu 4137333Sgblack@eecs.umich.edu # 4147760SGiacomo.Gabrielli@arm.com # Must create the individual controllers before the network to ensure the 4157760SGiacomo.Gabrielli@arm.com # controller constructors are called before the network constructor 4167396Sgblack@eecs.umich.edu # 4177396Sgblack@eecs.umich.edu 4187333Sgblack@eecs.umich.edu # For an odd number of CPUs, still create the right number of controllers 4197333Sgblack@eecs.umich.edu TCC_bits = int(math.log(options.num_tccs, 2)) 4207640Sgblack@eecs.umich.edu 4217639Sgblack@eecs.umich.edu # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 4228588Sgblack@eecs.umich.edu # Clusters 4237333Sgblack@eecs.umich.edu crossbar_bw = None 4247396Sgblack@eecs.umich.edu mainCluster = None 4257333Sgblack@eecs.umich.edu if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 4267760SGiacomo.Gabrielli@arm.com #Assuming a 2GHz clock 4277760SGiacomo.Gabrielli@arm.com crossbar_bw = 16 * options.num_compute_units * options.bw_scalor 4287396Sgblack@eecs.umich.edu mainCluster = Cluster(intBW=crossbar_bw) 4297396Sgblack@eecs.umich.edu else: 4307333Sgblack@eecs.umich.edu mainCluster = Cluster(intBW=8) # 16 GB/s 4317333Sgblack@eecs.umich.edu for i in xrange(options.num_dirs): 4327640Sgblack@eecs.umich.edu 4338588Sgblack@eecs.umich.edu dir_cntrl = DirCntrl(noTCCdir = True, TCC_select_num_bits = TCC_bits) 4347333Sgblack@eecs.umich.edu dir_cntrl.create(options, ruby_system, system) 4357396Sgblack@eecs.umich.edu dir_cntrl.number_of_TBEs = options.num_tbes 4367333Sgblack@eecs.umich.edu dir_cntrl.useL3OnWT = options.use_L3_on_WT 4377760SGiacomo.Gabrielli@arm.com # the number_of_TBEs is inclusive of TBEs below 4387760SGiacomo.Gabrielli@arm.com 4397396Sgblack@eecs.umich.edu # Connect the Directory controller to the ruby network 4407396Sgblack@eecs.umich.edu dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 4417333Sgblack@eecs.umich.edu dir_cntrl.requestFromCores.slave = ruby_system.network.master 4427333Sgblack@eecs.umich.edu 4437640Sgblack@eecs.umich.edu dir_cntrl.responseFromCores = MessageBuffer() 4448588Sgblack@eecs.umich.edu dir_cntrl.responseFromCores.slave = ruby_system.network.master 4458588Sgblack@eecs.umich.edu 4467333Sgblack@eecs.umich.edu dir_cntrl.unblockFromCores = MessageBuffer() 4477396Sgblack@eecs.umich.edu dir_cntrl.unblockFromCores.slave = ruby_system.network.master 4487333Sgblack@eecs.umich.edu 4497760SGiacomo.Gabrielli@arm.com dir_cntrl.probeToCore = MessageBuffer() 4507760SGiacomo.Gabrielli@arm.com dir_cntrl.probeToCore.master = ruby_system.network.slave 4517396Sgblack@eecs.umich.edu 4527396Sgblack@eecs.umich.edu dir_cntrl.responseToCore = MessageBuffer() 4537333Sgblack@eecs.umich.edu dir_cntrl.responseToCore.master = ruby_system.network.slave 4547333Sgblack@eecs.umich.edu 4557640Sgblack@eecs.umich.edu dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 4568588Sgblack@eecs.umich.edu dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 4578588Sgblack@eecs.umich.edu dir_cntrl.responseFromMemory = MessageBuffer() 4587333Sgblack@eecs.umich.edu 4597396Sgblack@eecs.umich.edu exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 4607333Sgblack@eecs.umich.edu dir_cntrl_nodes.append(dir_cntrl) 4617760SGiacomo.Gabrielli@arm.com 4627760SGiacomo.Gabrielli@arm.com mainCluster.add(dir_cntrl) 4637396Sgblack@eecs.umich.edu 4647396Sgblack@eecs.umich.edu cpuCluster = None 4657333Sgblack@eecs.umich.edu if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 4667381Sgblack@eecs.umich.edu cpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) 4677381Sgblack@eecs.umich.edu else: 4687381Sgblack@eecs.umich.edu cpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s 4697381Sgblack@eecs.umich.edu for i in xrange((options.num_cpus + 1) / 2): 4707381Sgblack@eecs.umich.edu 4717381Sgblack@eecs.umich.edu cp_cntrl = CPCntrl() 4727381Sgblack@eecs.umich.edu cp_cntrl.create(options, ruby_system, system) 4737364Sgblack@eecs.umich.edu 4747783SGiacomo.Gabrielli@arm.com exec("ruby_system.cp_cntrl%d = cp_cntrl" % i) 4758607Sgblack@eecs.umich.edu # 4767396Sgblack@eecs.umich.edu # Add controllers and sequencers to the appropriate lists 4777783SGiacomo.Gabrielli@arm.com # 4787783SGiacomo.Gabrielli@arm.com cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 4797783SGiacomo.Gabrielli@arm.com 4807364Sgblack@eecs.umich.edu # Connect the CP controllers and the network 48110037SARM gem5 Developers cp_cntrl.requestFromCore = MessageBuffer() 48210037SARM gem5 Developers cp_cntrl.requestFromCore.master = ruby_system.network.slave 48310037SARM gem5 Developers 48410037SARM gem5 Developers cp_cntrl.responseFromCore = MessageBuffer() 48510037SARM gem5 Developers cp_cntrl.responseFromCore.master = ruby_system.network.slave 48610037SARM gem5 Developers 48710037SARM gem5 Developers cp_cntrl.unblockFromCore = MessageBuffer() 48810037SARM gem5 Developers cp_cntrl.unblockFromCore.master = ruby_system.network.slave 48910037SARM gem5 Developers 49010037SARM gem5 Developers cp_cntrl.probeToCore = MessageBuffer() 49110037SARM gem5 Developers cp_cntrl.probeToCore.slave = ruby_system.network.master 4927396Sgblack@eecs.umich.edu 4937639Sgblack@eecs.umich.edu cp_cntrl.responseToCore = MessageBuffer() 4947396Sgblack@eecs.umich.edu cp_cntrl.responseToCore.slave = ruby_system.network.master 4957640Sgblack@eecs.umich.edu 4968607Sgblack@eecs.umich.edu cp_cntrl.mandatoryQueue = MessageBuffer() 4977396Sgblack@eecs.umich.edu cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 4988588Sgblack@eecs.umich.edu 4998588Sgblack@eecs.umich.edu cpuCluster.add(cp_cntrl) 5007783SGiacomo.Gabrielli@arm.com 5017396Sgblack@eecs.umich.edu gpuCluster = None 50210037SARM gem5 Developers if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 50310037SARM gem5 Developers gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) 50410037SARM gem5 Developers else: 50510037SARM gem5 Developers gpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s 50610037SARM gem5 Developers for i in xrange(options.num_compute_units): 50710037SARM gem5 Developers 50810037SARM gem5 Developers tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 50910037SARM gem5 Developers issue_latency = 1, 51010037SARM gem5 Developers number_of_TBEs = 2560) 51110037SARM gem5 Developers # TBEs set to max outstanding requests 51210037SARM gem5 Developers tcp_cntrl.create(options, ruby_system, system) 51310037SARM gem5 Developers tcp_cntrl.WB = options.WB_L1 51410037SARM gem5 Developers tcp_cntrl.disableL1 = options.noL1 5157396Sgblack@eecs.umich.edu tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency 5168588Sgblack@eecs.umich.edu tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency 5178588Sgblack@eecs.umich.edu 5187639Sgblack@eecs.umich.edu exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % i) 5197396Sgblack@eecs.umich.edu # 5207396Sgblack@eecs.umich.edu # Add controllers and sequencers to the appropriate lists 5218588Sgblack@eecs.umich.edu # 5227396Sgblack@eecs.umich.edu cpu_sequencers.append(tcp_cntrl.coalescer) 5237396Sgblack@eecs.umich.edu tcp_cntrl_nodes.append(tcp_cntrl) 5247364Sgblack@eecs.umich.edu 52510037SARM gem5 Developers # Connect the TCP controller to the ruby network 52610037SARM gem5 Developers tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 52710037SARM gem5 Developers tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 52810037SARM gem5 Developers 52910037SARM gem5 Developers tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 53010037SARM gem5 Developers tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 53110037SARM gem5 Developers 53210037SARM gem5 Developers tcp_cntrl.unblockFromCore = MessageBuffer() 53310037SARM gem5 Developers tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 53410037SARM gem5 Developers 53510037SARM gem5 Developers tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 53610037SARM gem5 Developers tcp_cntrl.probeToTCP.slave = ruby_system.network.master 53710037SARM gem5 Developers 53810037SARM gem5 Developers tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 53910037SARM gem5 Developers tcp_cntrl.responseToTCP.slave = ruby_system.network.master 54010037SARM gem5 Developers 54110037SARM gem5 Developers tcp_cntrl.mandatoryQueue = MessageBuffer() 54210037SARM gem5 Developers 54310037SARM gem5 Developers gpuCluster.add(tcp_cntrl) 54410037SARM gem5 Developers 54510037SARM gem5 Developers for i in xrange(options.num_sqc): 54610037SARM gem5 Developers 54710037SARM gem5 Developers sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 54810037SARM gem5 Developers sqc_cntrl.create(options, ruby_system, system) 54910037SARM gem5 Developers 55010037SARM gem5 Developers exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % i) 55110037SARM gem5 Developers # 55210037SARM gem5 Developers # Add controllers and sequencers to the appropriate lists 55310037SARM gem5 Developers # 55410037SARM gem5 Developers cpu_sequencers.append(sqc_cntrl.sequencer) 55510037SARM gem5 Developers 5567760SGiacomo.Gabrielli@arm.com # Connect the SQC controller to the ruby network 5577396Sgblack@eecs.umich.edu sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 5587365Sgblack@eecs.umich.edu sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 5597396Sgblack@eecs.umich.edu 5607396Sgblack@eecs.umich.edu sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 5617396Sgblack@eecs.umich.edu sqc_cntrl.probeToSQC.slave = ruby_system.network.master 5627760SGiacomo.Gabrielli@arm.com 5637760SGiacomo.Gabrielli@arm.com sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 5647760SGiacomo.Gabrielli@arm.com sqc_cntrl.responseToSQC.slave = ruby_system.network.master 5657396Sgblack@eecs.umich.edu 5667396Sgblack@eecs.umich.edu sqc_cntrl.mandatoryQueue = MessageBuffer() 5677396Sgblack@eecs.umich.edu 5687760SGiacomo.Gabrielli@arm.com # SQC also in GPU cluster 5697760SGiacomo.Gabrielli@arm.com gpuCluster.add(sqc_cntrl) 5707760SGiacomo.Gabrielli@arm.com 5717365Sgblack@eecs.umich.edu for i in xrange(options.num_cp): 5727396Sgblack@eecs.umich.edu 5737396Sgblack@eecs.umich.edu tcp_ID = options.num_compute_units + i 5747366Sgblack@eecs.umich.edu sqc_ID = options.num_sqc + i 5757396Sgblack@eecs.umich.edu 5767396Sgblack@eecs.umich.edu tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 5777396Sgblack@eecs.umich.edu issue_latency = 1, 5787396Sgblack@eecs.umich.edu number_of_TBEs = 2560) 5797366Sgblack@eecs.umich.edu # TBEs set to max outstanding requests 5807760SGiacomo.Gabrielli@arm.com tcp_cntrl.createCP(options, ruby_system, system) 5817760SGiacomo.Gabrielli@arm.com tcp_cntrl.WB = options.WB_L1 5827760SGiacomo.Gabrielli@arm.com tcp_cntrl.disableL1 = options.noL1 5837760SGiacomo.Gabrielli@arm.com tcp_cntrl.L1cache.tagAccessLatency = options.TCP_latency 5847760SGiacomo.Gabrielli@arm.com tcp_cntrl.L1cache.dataAccessLatency = options.TCP_latency 5857760SGiacomo.Gabrielli@arm.com 5867760SGiacomo.Gabrielli@arm.com exec("ruby_system.tcp_cntrl%d = tcp_cntrl" % tcp_ID) 5877760SGiacomo.Gabrielli@arm.com # 5887367Sgblack@eecs.umich.edu # Add controllers and sequencers to the appropriate lists 5897760SGiacomo.Gabrielli@arm.com # 5907396Sgblack@eecs.umich.edu cpu_sequencers.append(tcp_cntrl.sequencer) 5917396Sgblack@eecs.umich.edu tcp_cntrl_nodes.append(tcp_cntrl) 5927396Sgblack@eecs.umich.edu 5937367Sgblack@eecs.umich.edu # Connect the CP (TCP) controllers to the ruby network 5947396Sgblack@eecs.umich.edu tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 5957396Sgblack@eecs.umich.edu tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 5967396Sgblack@eecs.umich.edu 5977760SGiacomo.Gabrielli@arm.com tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 5987760SGiacomo.Gabrielli@arm.com tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 5997760SGiacomo.Gabrielli@arm.com 6007396Sgblack@eecs.umich.edu tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True) 6017396Sgblack@eecs.umich.edu tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 6027396Sgblack@eecs.umich.edu 6037760SGiacomo.Gabrielli@arm.com tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 6047760SGiacomo.Gabrielli@arm.com tcp_cntrl.probeToTCP.slave = ruby_system.network.master 6057760SGiacomo.Gabrielli@arm.com 6067368Sgblack@eecs.umich.edu tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 6077396Sgblack@eecs.umich.edu tcp_cntrl.responseToTCP.slave = ruby_system.network.master 6087396Sgblack@eecs.umich.edu 6097368Sgblack@eecs.umich.edu tcp_cntrl.mandatoryQueue = MessageBuffer() 6107396Sgblack@eecs.umich.edu 6117396Sgblack@eecs.umich.edu gpuCluster.add(tcp_cntrl) 6127396Sgblack@eecs.umich.edu 6137396Sgblack@eecs.umich.edu sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 6147369Sgblack@eecs.umich.edu sqc_cntrl.create(options, ruby_system, system) 6157760SGiacomo.Gabrielli@arm.com 6167760SGiacomo.Gabrielli@arm.com exec("ruby_system.sqc_cntrl%d = sqc_cntrl" % sqc_ID) 6177369Sgblack@eecs.umich.edu # 6187760SGiacomo.Gabrielli@arm.com # Add controllers and sequencers to the appropriate lists 6197760SGiacomo.Gabrielli@arm.com # 6207396Sgblack@eecs.umich.edu cpu_sequencers.append(sqc_cntrl.sequencer) 6217396Sgblack@eecs.umich.edu 6227396Sgblack@eecs.umich.edu # SQC also in GPU cluster 6237369Sgblack@eecs.umich.edu gpuCluster.add(sqc_cntrl) 6247396Sgblack@eecs.umich.edu 6257783SGiacomo.Gabrielli@arm.com for i in xrange(options.num_tccs): 6267760SGiacomo.Gabrielli@arm.com 6277760SGiacomo.Gabrielli@arm.com tcc_cntrl = TCCCntrl(l2_response_latency = options.TCC_latency) 6287396Sgblack@eecs.umich.edu tcc_cntrl.create(options, ruby_system, system) 6297396Sgblack@eecs.umich.edu tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 6307760SGiacomo.Gabrielli@arm.com tcc_cntrl.l2_response_latency = options.TCC_latency 6317760SGiacomo.Gabrielli@arm.com tcc_cntrl_nodes.append(tcc_cntrl) 6327369Sgblack@eecs.umich.edu tcc_cntrl.WB = options.WB_L2 6337396Sgblack@eecs.umich.edu tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units 6347396Sgblack@eecs.umich.edu # the number_of_TBEs is inclusive of TBEs below 6357396Sgblack@eecs.umich.edu 6367396Sgblack@eecs.umich.edu # Connect the TCC controllers to the ruby network 6377396Sgblack@eecs.umich.edu tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True) 6387396Sgblack@eecs.umich.edu tcc_cntrl.requestFromTCP.slave = ruby_system.network.master 6397396Sgblack@eecs.umich.edu 6407396Sgblack@eecs.umich.edu tcc_cntrl.responseToCore = MessageBuffer(ordered = True) 6417760SGiacomo.Gabrielli@arm.com tcc_cntrl.responseToCore.master = ruby_system.network.slave 6428588Sgblack@eecs.umich.edu 6437760SGiacomo.Gabrielli@arm.com tcc_cntrl.probeFromNB = MessageBuffer() 6448588Sgblack@eecs.umich.edu tcc_cntrl.probeFromNB.slave = ruby_system.network.master 6457381Sgblack@eecs.umich.edu 6467381Sgblack@eecs.umich.edu tcc_cntrl.responseFromNB = MessageBuffer() 6477381Sgblack@eecs.umich.edu tcc_cntrl.responseFromNB.slave = ruby_system.network.master 6487381Sgblack@eecs.umich.edu 6497381Sgblack@eecs.umich.edu tcc_cntrl.requestToNB = MessageBuffer(ordered = True) 6507381Sgblack@eecs.umich.edu tcc_cntrl.requestToNB.master = ruby_system.network.slave 6517381Sgblack@eecs.umich.edu 6527370Sgblack@eecs.umich.edu tcc_cntrl.responseToNB = MessageBuffer() 6537640Sgblack@eecs.umich.edu tcc_cntrl.responseToNB.master = ruby_system.network.slave 6547783SGiacomo.Gabrielli@arm.com 6557396Sgblack@eecs.umich.edu tcc_cntrl.unblockToNB = MessageBuffer() 6567639Sgblack@eecs.umich.edu tcc_cntrl.unblockToNB.master = ruby_system.network.slave 6577639Sgblack@eecs.umich.edu 6587639Sgblack@eecs.umich.edu tcc_cntrl.triggerQueue = MessageBuffer(ordered = True) 6597783SGiacomo.Gabrielli@arm.com 6607370Sgblack@eecs.umich.edu exec("ruby_system.tcc_cntrl%d = tcc_cntrl" % i) 6617396Sgblack@eecs.umich.edu 6627370Sgblack@eecs.umich.edu # connect all of the wire buffers between L3 and dirs up 6637760SGiacomo.Gabrielli@arm.com # TCC cntrls added to the GPU cluster 6647760SGiacomo.Gabrielli@arm.com gpuCluster.add(tcc_cntrl) 6657396Sgblack@eecs.umich.edu 6667396Sgblack@eecs.umich.edu # Assuming no DMA devices 6677370Sgblack@eecs.umich.edu assert(len(dma_devices) == 0) 6687370Sgblack@eecs.umich.edu 6697640Sgblack@eecs.umich.edu # Add cpu/gpu clusters to main cluster 6707783SGiacomo.Gabrielli@arm.com mainCluster.add(cpuCluster) 6718588Sgblack@eecs.umich.edu mainCluster.add(gpuCluster) 6728588Sgblack@eecs.umich.edu 6737639Sgblack@eecs.umich.edu ruby_system.network.number_of_virtual_networks = 10 6748588Sgblack@eecs.umich.edu 6757639Sgblack@eecs.umich.edu return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 6767639Sgblack@eecs.umich.edu