GPU_RfO.py revision 13731
110802Srene.dejong@arm.com# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 210802Srene.dejong@arm.com# All rights reserved. 310802Srene.dejong@arm.com# 410802Srene.dejong@arm.com# For use for simulation and test purposes only 510802Srene.dejong@arm.com# 610802Srene.dejong@arm.com# Redistribution and use in source and binary forms, with or without 710802Srene.dejong@arm.com# modification, are permitted provided that the following conditions are met: 810802Srene.dejong@arm.com# 910802Srene.dejong@arm.com# 1. Redistributions of source code must retain the above copyright notice, 1010802Srene.dejong@arm.com# this list of conditions and the following disclaimer. 1110802Srene.dejong@arm.com# 1210802Srene.dejong@arm.com# 2. Redistributions in binary form must reproduce the above copyright notice, 1310802Srene.dejong@arm.com# this list of conditions and the following disclaimer in the documentation 1410802Srene.dejong@arm.com# and/or other materials provided with the distribution. 1510802Srene.dejong@arm.com# 1610802Srene.dejong@arm.com# 3. Neither the name of the copyright holder nor the names of its 1710802Srene.dejong@arm.com# contributors may be used to endorse or promote products derived from this 1810802Srene.dejong@arm.com# software without specific prior written permission. 1910802Srene.dejong@arm.com# 2010802Srene.dejong@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2110802Srene.dejong@arm.com# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2210802Srene.dejong@arm.com# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2310802Srene.dejong@arm.com# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2410802Srene.dejong@arm.com# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2510802Srene.dejong@arm.com# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2610802Srene.dejong@arm.com# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2710802Srene.dejong@arm.com# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2810802Srene.dejong@arm.com# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2910802Srene.dejong@arm.com# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3010802Srene.dejong@arm.com# POSSIBILITY OF SUCH DAMAGE. 3110802Srene.dejong@arm.com# 3210802Srene.dejong@arm.com# Authors: Lisa Hsu 3310802Srene.dejong@arm.com 3410802Srene.dejong@arm.comimport math 3510802Srene.dejong@arm.comimport m5 3610802Srene.dejong@arm.comfrom m5.objects import * 3710802Srene.dejong@arm.comfrom m5.defines import buildEnv 3810802Srene.dejong@arm.comfrom m5.util import addToPath 3910802Srene.dejong@arm.comfrom Ruby import create_topology 4010802Srene.dejong@arm.comfrom Ruby import send_evicts 4110802Srene.dejong@arm.com 4210802Srene.dejong@arm.comaddToPath('../') 4310802Srene.dejong@arm.com 4410802Srene.dejong@arm.comfrom topologies.Cluster import Cluster 4510802Srene.dejong@arm.comfrom topologies.Crossbar import Crossbar 4610802Srene.dejong@arm.com 4710802Srene.dejong@arm.comclass CntrlBase: 4810802Srene.dejong@arm.com _seqs = 0 4910802Srene.dejong@arm.com @classmethod 5010802Srene.dejong@arm.com def seqCount(cls): 5110802Srene.dejong@arm.com # Use SeqCount not class since we need global count 5210802Srene.dejong@arm.com CntrlBase._seqs += 1 5310802Srene.dejong@arm.com return CntrlBase._seqs - 1 5410802Srene.dejong@arm.com 5510802Srene.dejong@arm.com _cntrls = 0 5610802Srene.dejong@arm.com @classmethod 5710802Srene.dejong@arm.com def cntrlCount(cls): 5810802Srene.dejong@arm.com # Use CntlCount not class since we need global count 5910802Srene.dejong@arm.com CntrlBase._cntrls += 1 6010802Srene.dejong@arm.com return CntrlBase._cntrls - 1 6110802Srene.dejong@arm.com 6210802Srene.dejong@arm.com _version = 0 6310802Srene.dejong@arm.com @classmethod 6410802Srene.dejong@arm.com def versionCount(cls): 6510802Srene.dejong@arm.com cls._version += 1 # Use count for this particular type 6610802Srene.dejong@arm.com return cls._version - 1 6710802Srene.dejong@arm.com 6810802Srene.dejong@arm.comclass TccDirCache(RubyCache): 6910802Srene.dejong@arm.com size = "512kB" 7010802Srene.dejong@arm.com assoc = 16 7110802Srene.dejong@arm.com resourceStalls = False 7210802Srene.dejong@arm.com def create(self, options): 7310802Srene.dejong@arm.com self.size = MemorySize(options.tcc_size) 7410802Srene.dejong@arm.com self.size.value += (options.num_compute_units * 7510802Srene.dejong@arm.com (MemorySize(options.tcp_size).value) * 7610802Srene.dejong@arm.com options.tcc_dir_factor) / long(options.num_tccs) 7710802Srene.dejong@arm.com self.start_index_bit = math.log(options.cacheline_size, 2) + \ 7810802Srene.dejong@arm.com math.log(options.num_tccs, 2) 7910802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 8010802Srene.dejong@arm.com 8110802Srene.dejong@arm.comclass L1DCache(RubyCache): 8210802Srene.dejong@arm.com resourceStalls = False 8310802Srene.dejong@arm.com def create(self, options): 8410802Srene.dejong@arm.com self.size = MemorySize(options.l1d_size) 8510802Srene.dejong@arm.com self.assoc = options.l1d_assoc 8610802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 8710802Srene.dejong@arm.com 8810802Srene.dejong@arm.comclass L1ICache(RubyCache): 8910802Srene.dejong@arm.com resourceStalls = False 9010802Srene.dejong@arm.com def create(self, options): 9110802Srene.dejong@arm.com self.size = MemorySize(options.l1i_size) 9210802Srene.dejong@arm.com self.assoc = options.l1i_assoc 9310802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 9410802Srene.dejong@arm.com 9510802Srene.dejong@arm.comclass L2Cache(RubyCache): 9610802Srene.dejong@arm.com resourceStalls = False 9710802Srene.dejong@arm.com def create(self, options): 9810802Srene.dejong@arm.com self.size = MemorySize(options.l2_size) 9910802Srene.dejong@arm.com self.assoc = options.l2_assoc 10010802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 10110802Srene.dejong@arm.com 10210802Srene.dejong@arm.com 10310802Srene.dejong@arm.comclass CPCntrl(CorePair_Controller, CntrlBase): 10410802Srene.dejong@arm.com 10510802Srene.dejong@arm.com def create(self, options, ruby_system, system): 10610802Srene.dejong@arm.com self.version = self.versionCount() 10710802Srene.dejong@arm.com 10810802Srene.dejong@arm.com self.L1Icache = L1ICache() 10910802Srene.dejong@arm.com self.L1Icache.create(options) 11010802Srene.dejong@arm.com self.L1D0cache = L1DCache() 11110802Srene.dejong@arm.com self.L1D0cache.create(options) 11210802Srene.dejong@arm.com self.L1D1cache = L1DCache() 11310802Srene.dejong@arm.com self.L1D1cache.create(options) 11410802Srene.dejong@arm.com self.L2cache = L2Cache() 11510802Srene.dejong@arm.com self.L2cache.create(options) 11610802Srene.dejong@arm.com 11710802Srene.dejong@arm.com self.sequencer = RubySequencer() 11810802Srene.dejong@arm.com self.sequencer.icache_hit_latency = 2 11910802Srene.dejong@arm.com self.sequencer.dcache_hit_latency = 2 12010802Srene.dejong@arm.com self.sequencer.version = self.seqCount() 12110802Srene.dejong@arm.com self.sequencer.icache = self.L1Icache 12210802Srene.dejong@arm.com self.sequencer.dcache = self.L1D0cache 12310802Srene.dejong@arm.com self.sequencer.ruby_system = ruby_system 12410802Srene.dejong@arm.com self.sequencer.coreid = 0 12510802Srene.dejong@arm.com self.sequencer.is_cpu_sequencer = True 12610802Srene.dejong@arm.com 12710802Srene.dejong@arm.com self.sequencer1 = RubySequencer() 12810802Srene.dejong@arm.com self.sequencer1.version = self.seqCount() 12910802Srene.dejong@arm.com self.sequencer1.icache = self.L1Icache 13010802Srene.dejong@arm.com self.sequencer1.dcache = self.L1D1cache 13110802Srene.dejong@arm.com self.sequencer1.icache_hit_latency = 2 13210802Srene.dejong@arm.com self.sequencer1.dcache_hit_latency = 2 13310802Srene.dejong@arm.com self.sequencer1.ruby_system = ruby_system 13410802Srene.dejong@arm.com self.sequencer1.coreid = 1 13510802Srene.dejong@arm.com self.sequencer1.is_cpu_sequencer = True 13610802Srene.dejong@arm.com 13710802Srene.dejong@arm.com self.issue_latency = options.cpu_to_dir_latency 13810802Srene.dejong@arm.com self.send_evictions = send_evicts(options) 13910802Srene.dejong@arm.com 14010802Srene.dejong@arm.com self.ruby_system = ruby_system 14110802Srene.dejong@arm.com 14210802Srene.dejong@arm.com if options.recycle_latency: 14310802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 14410802Srene.dejong@arm.com 14510802Srene.dejong@arm.comclass TCPCache(RubyCache): 14610802Srene.dejong@arm.com assoc = 8 14710802Srene.dejong@arm.com dataArrayBanks = 16 14810802Srene.dejong@arm.com tagArrayBanks = 4 14910802Srene.dejong@arm.com dataAccessLatency = 4 15010802Srene.dejong@arm.com tagAccessLatency = 1 15110802Srene.dejong@arm.com def create(self, options): 15210802Srene.dejong@arm.com self.size = MemorySize(options.tcp_size) 15310802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 15410802Srene.dejong@arm.com 15510802Srene.dejong@arm.comclass TCPCntrl(TCP_Controller, CntrlBase): 15610802Srene.dejong@arm.com 15710802Srene.dejong@arm.com def create(self, options, ruby_system, system): 15810802Srene.dejong@arm.com self.version = self.versionCount() 15910802Srene.dejong@arm.com 16010802Srene.dejong@arm.com self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency) 16110802Srene.dejong@arm.com self.L1cache.resourceStalls = options.no_resource_stalls 16210802Srene.dejong@arm.com self.L1cache.create(options) 16310802Srene.dejong@arm.com 16410802Srene.dejong@arm.com self.coalescer = RubyGPUCoalescer() 16510802Srene.dejong@arm.com self.coalescer.version = self.seqCount() 16610802Srene.dejong@arm.com self.coalescer.icache = self.L1cache 16710802Srene.dejong@arm.com self.coalescer.dcache = self.L1cache 16810802Srene.dejong@arm.com self.coalescer.ruby_system = ruby_system 16910802Srene.dejong@arm.com self.coalescer.support_inst_reqs = False 17010802Srene.dejong@arm.com self.coalescer.is_cpu_sequencer = False 17110802Srene.dejong@arm.com self.coalescer.max_outstanding_requests = options.simds_per_cu * \ 17210802Srene.dejong@arm.com options.wfs_per_simd * \ 17310802Srene.dejong@arm.com options.wf_size 17410802Srene.dejong@arm.com 17510802Srene.dejong@arm.com self.sequencer = RubySequencer() 17610802Srene.dejong@arm.com self.sequencer.version = self.seqCount() 17710802Srene.dejong@arm.com self.sequencer.icache = self.L1cache 17810802Srene.dejong@arm.com self.sequencer.dcache = self.L1cache 17910802Srene.dejong@arm.com self.sequencer.ruby_system = ruby_system 18010802Srene.dejong@arm.com self.sequencer.is_cpu_sequencer = True 18110802Srene.dejong@arm.com 18210802Srene.dejong@arm.com self.use_seq_not_coal = False 18310802Srene.dejong@arm.com 18410802Srene.dejong@arm.com self.ruby_system = ruby_system 18510802Srene.dejong@arm.com 18610802Srene.dejong@arm.com if options.recycle_latency: 18710802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 18810802Srene.dejong@arm.com 18910802Srene.dejong@arm.com def createCP(self, options, ruby_system, system): 19010802Srene.dejong@arm.com self.version = self.versionCount() 19110802Srene.dejong@arm.com 19210802Srene.dejong@arm.com self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency) 19310802Srene.dejong@arm.com self.L1cache.resourceStalls = options.no_resource_stalls 19410802Srene.dejong@arm.com self.L1cache.create(options) 19510802Srene.dejong@arm.com 19610802Srene.dejong@arm.com self.coalescer = RubyGPUCoalescer() 19710802Srene.dejong@arm.com self.coalescer.version = self.seqCount() 19810802Srene.dejong@arm.com self.coalescer.icache = self.L1cache 19910802Srene.dejong@arm.com self.coalescer.dcache = self.L1cache 20010802Srene.dejong@arm.com self.coalescer.ruby_system = ruby_system 20110802Srene.dejong@arm.com self.coalescer.support_inst_reqs = False 20210802Srene.dejong@arm.com self.coalescer.is_cpu_sequencer = False 20310802Srene.dejong@arm.com 20410802Srene.dejong@arm.com self.sequencer = RubySequencer() 20510802Srene.dejong@arm.com self.sequencer.version = self.seqCount() 20610802Srene.dejong@arm.com self.sequencer.icache = self.L1cache 20710802Srene.dejong@arm.com self.sequencer.dcache = self.L1cache 20810802Srene.dejong@arm.com self.sequencer.ruby_system = ruby_system 20910802Srene.dejong@arm.com self.sequencer.is_cpu_sequencer = True 21010802Srene.dejong@arm.com 21110802Srene.dejong@arm.com self.use_seq_not_coal = True 21210802Srene.dejong@arm.com 21310802Srene.dejong@arm.com self.ruby_system = ruby_system 21410802Srene.dejong@arm.com 21510802Srene.dejong@arm.com if options.recycle_latency: 21610802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 21710802Srene.dejong@arm.com 21810802Srene.dejong@arm.comclass SQCCache(RubyCache): 21910802Srene.dejong@arm.com size = "32kB" 22010802Srene.dejong@arm.com assoc = 8 22110802Srene.dejong@arm.com dataArrayBanks = 16 22210802Srene.dejong@arm.com tagArrayBanks = 4 22310802Srene.dejong@arm.com dataAccessLatency = 4 22410802Srene.dejong@arm.com tagAccessLatency = 1 22510802Srene.dejong@arm.com def create(self, options): 22610802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 22710802Srene.dejong@arm.com 22810802Srene.dejong@arm.comclass SQCCntrl(SQC_Controller, CntrlBase): 22910802Srene.dejong@arm.com 23010802Srene.dejong@arm.com def create(self, options, ruby_system, system): 23110802Srene.dejong@arm.com self.version = self.versionCount() 23210802Srene.dejong@arm.com 23310802Srene.dejong@arm.com self.L1cache = SQCCache() 23410802Srene.dejong@arm.com self.L1cache.create(options) 23510802Srene.dejong@arm.com self.L1cache.resourceStalls = options.no_resource_stalls 23610802Srene.dejong@arm.com 23710802Srene.dejong@arm.com self.sequencer = RubySequencer() 23810802Srene.dejong@arm.com 23910802Srene.dejong@arm.com self.sequencer.version = self.seqCount() 24010802Srene.dejong@arm.com self.sequencer.icache = self.L1cache 24110802Srene.dejong@arm.com self.sequencer.dcache = self.L1cache 24210802Srene.dejong@arm.com self.sequencer.ruby_system = ruby_system 24310802Srene.dejong@arm.com self.sequencer.support_data_reqs = False 24410802Srene.dejong@arm.com self.sequencer.is_cpu_sequencer = False 24510802Srene.dejong@arm.com 24610802Srene.dejong@arm.com self.ruby_system = ruby_system 24710802Srene.dejong@arm.com 24810802Srene.dejong@arm.com if options.recycle_latency: 24910802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 25010802Srene.dejong@arm.com 25110802Srene.dejong@arm.com def createCP(self, options, ruby_system, system): 25210802Srene.dejong@arm.com self.version = self.versionCount() 25310802Srene.dejong@arm.com 25410802Srene.dejong@arm.com self.L1cache = SQCCache() 25510802Srene.dejong@arm.com self.L1cache.create(options) 25610802Srene.dejong@arm.com self.L1cache.resourceStalls = options.no_resource_stalls 25710802Srene.dejong@arm.com 25810802Srene.dejong@arm.com self.sequencer = RubySequencer() 25910802Srene.dejong@arm.com 26010802Srene.dejong@arm.com self.sequencer.version = self.seqCount() 26110802Srene.dejong@arm.com self.sequencer.icache = self.L1cache 26210802Srene.dejong@arm.com self.sequencer.dcache = self.L1cache 26310802Srene.dejong@arm.com self.sequencer.ruby_system = ruby_system 26410802Srene.dejong@arm.com self.sequencer.support_data_reqs = False 26510802Srene.dejong@arm.com 26610802Srene.dejong@arm.com self.ruby_system = ruby_system 26710802Srene.dejong@arm.com 26810802Srene.dejong@arm.com if options.recycle_latency: 26910802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 27010802Srene.dejong@arm.com 27110802Srene.dejong@arm.com 27210802Srene.dejong@arm.comclass TCC(RubyCache): 27310802Srene.dejong@arm.com assoc = 16 27410802Srene.dejong@arm.com dataAccessLatency = 8 27510802Srene.dejong@arm.com tagAccessLatency = 2 27610802Srene.dejong@arm.com resourceStalls = True 27710802Srene.dejong@arm.com def create(self, options): 27810802Srene.dejong@arm.com self.size = MemorySize(options.tcc_size) 27910802Srene.dejong@arm.com self.size = self.size / options.num_tccs 28010802Srene.dejong@arm.com self.dataArrayBanks = 256 / options.num_tccs #number of data banks 28110802Srene.dejong@arm.com self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 28210802Srene.dejong@arm.com if ((self.size.value / long(self.assoc)) < 128): 28310802Srene.dejong@arm.com self.size.value = long(128 * self.assoc) 28410802Srene.dejong@arm.com self.start_index_bit = math.log(options.cacheline_size, 2) + \ 28510802Srene.dejong@arm.com math.log(options.num_tccs, 2) 28610802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 28710802Srene.dejong@arm.com 28810802Srene.dejong@arm.comclass TCCCntrl(TCC_Controller, CntrlBase): 28910802Srene.dejong@arm.com def create(self, options, ruby_system, system): 29010802Srene.dejong@arm.com self.version = self.versionCount() 29110802Srene.dejong@arm.com self.L2cache = TCC() 29210802Srene.dejong@arm.com self.L2cache.create(options) 29310802Srene.dejong@arm.com self.l2_response_latency = options.TCC_latency 29410802Srene.dejong@arm.com 29510802Srene.dejong@arm.com self.number_of_TBEs = 2048 29610802Srene.dejong@arm.com 29710802Srene.dejong@arm.com self.ruby_system = ruby_system 29810802Srene.dejong@arm.com 29910802Srene.dejong@arm.com if options.recycle_latency: 30010802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 30110802Srene.dejong@arm.com 30210802Srene.dejong@arm.com def connectWireBuffers(self, req_to_tccdir, resp_to_tccdir, 30310802Srene.dejong@arm.com tcc_unblock_to_tccdir, req_to_tcc, 30410802Srene.dejong@arm.com probe_to_tcc, resp_to_tcc): 30510802Srene.dejong@arm.com self.w_reqToTCCDir = req_to_tccdir 30610802Srene.dejong@arm.com self.w_respToTCCDir = resp_to_tccdir 30710802Srene.dejong@arm.com self.w_TCCUnblockToTCCDir = tcc_unblock_to_tccdir 30810802Srene.dejong@arm.com self.w_reqToTCC = req_to_tcc 30910802Srene.dejong@arm.com self.w_probeToTCC = probe_to_tcc 31010802Srene.dejong@arm.com self.w_respToTCC = resp_to_tcc 31110802Srene.dejong@arm.com 31210802Srene.dejong@arm.comclass TCCDirCntrl(TCCdir_Controller, CntrlBase): 31310802Srene.dejong@arm.com def create(self, options, ruby_system, system): 31410802Srene.dejong@arm.com self.version = self.versionCount() 31510802Srene.dejong@arm.com 31610802Srene.dejong@arm.com self.directory = TccDirCache() 31710802Srene.dejong@arm.com self.directory.create(options) 31810802Srene.dejong@arm.com 31910802Srene.dejong@arm.com self.number_of_TBEs = 1024 32010802Srene.dejong@arm.com 32110802Srene.dejong@arm.com self.ruby_system = ruby_system 32210802Srene.dejong@arm.com 32310802Srene.dejong@arm.com if options.recycle_latency: 32410802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 32510802Srene.dejong@arm.com 32610802Srene.dejong@arm.com def connectWireBuffers(self, req_to_tccdir, resp_to_tccdir, 32710802Srene.dejong@arm.com tcc_unblock_to_tccdir, req_to_tcc, 32810802Srene.dejong@arm.com probe_to_tcc, resp_to_tcc): 32910802Srene.dejong@arm.com self.w_reqToTCCDir = req_to_tccdir 33010802Srene.dejong@arm.com self.w_respToTCCDir = resp_to_tccdir 33110802Srene.dejong@arm.com self.w_TCCUnblockToTCCDir = tcc_unblock_to_tccdir 33210802Srene.dejong@arm.com self.w_reqToTCC = req_to_tcc 33310802Srene.dejong@arm.com self.w_probeToTCC = probe_to_tcc 33410802Srene.dejong@arm.com self.w_respToTCC = resp_to_tcc 33510802Srene.dejong@arm.com 33610802Srene.dejong@arm.comclass L3Cache(RubyCache): 33710802Srene.dejong@arm.com assoc = 8 33810802Srene.dejong@arm.com dataArrayBanks = 256 33910802Srene.dejong@arm.com tagArrayBanks = 256 34010802Srene.dejong@arm.com 34110802Srene.dejong@arm.com def create(self, options, ruby_system, system): 34210802Srene.dejong@arm.com self.size = MemorySize(options.l3_size) 34310802Srene.dejong@arm.com self.size.value /= options.num_dirs 34410802Srene.dejong@arm.com self.dataArrayBanks /= options.num_dirs 34510802Srene.dejong@arm.com self.tagArrayBanks /= options.num_dirs 34610802Srene.dejong@arm.com self.dataArrayBanks /= options.num_dirs 34710802Srene.dejong@arm.com self.tagArrayBanks /= options.num_dirs 34810802Srene.dejong@arm.com self.dataAccessLatency = options.l3_data_latency 34910802Srene.dejong@arm.com self.tagAccessLatency = options.l3_tag_latency 35010802Srene.dejong@arm.com self.resourceStalls = options.no_resource_stalls 35110802Srene.dejong@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 35210802Srene.dejong@arm.com 35310802Srene.dejong@arm.comclass L3Cntrl(L3Cache_Controller, CntrlBase): 35410802Srene.dejong@arm.com def create(self, options, ruby_system, system): 35510802Srene.dejong@arm.com self.version = self.versionCount() 35610802Srene.dejong@arm.com self.L3cache = L3Cache() 35710802Srene.dejong@arm.com self.L3cache.create(options, ruby_system, system) 35810802Srene.dejong@arm.com 35910802Srene.dejong@arm.com self.l3_response_latency = max(self.L3cache.dataAccessLatency, 36010802Srene.dejong@arm.com self.L3cache.tagAccessLatency) 36110802Srene.dejong@arm.com self.ruby_system = ruby_system 36210802Srene.dejong@arm.com 36310802Srene.dejong@arm.com if options.recycle_latency: 36410802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 36510802Srene.dejong@arm.com 36610802Srene.dejong@arm.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 36710802Srene.dejong@arm.com req_to_l3, probe_to_l3, resp_to_l3): 36810802Srene.dejong@arm.com self.reqToDir = req_to_dir 36910802Srene.dejong@arm.com self.respToDir = resp_to_dir 37010802Srene.dejong@arm.com self.l3UnblockToDir = l3_unblock_to_dir 37110802Srene.dejong@arm.com self.reqToL3 = req_to_l3 37210802Srene.dejong@arm.com self.probeToL3 = probe_to_l3 37310802Srene.dejong@arm.com self.respToL3 = resp_to_l3 37410802Srene.dejong@arm.com 37510802Srene.dejong@arm.comclass DirCntrl(Directory_Controller, CntrlBase): 37610802Srene.dejong@arm.com def create(self, options, dir_ranges, ruby_system, system): 37710802Srene.dejong@arm.com self.version = self.versionCount() 37810802Srene.dejong@arm.com 37910802Srene.dejong@arm.com self.response_latency = 30 38010802Srene.dejong@arm.com 38110802Srene.dejong@arm.com self.addr_ranges = dir_ranges 38210802Srene.dejong@arm.com self.directory = RubyDirectoryMemory() 38310802Srene.dejong@arm.com 38410802Srene.dejong@arm.com self.L3CacheMemory = L3Cache() 38510802Srene.dejong@arm.com self.L3CacheMemory.create(options, ruby_system, system) 38610802Srene.dejong@arm.com 38710802Srene.dejong@arm.com self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 38810802Srene.dejong@arm.com self.L3CacheMemory.tagAccessLatency) 38910802Srene.dejong@arm.com 39010802Srene.dejong@arm.com self.number_of_TBEs = options.num_tbes 39110802Srene.dejong@arm.com 39210802Srene.dejong@arm.com self.ruby_system = ruby_system 39310802Srene.dejong@arm.com 39410802Srene.dejong@arm.com if options.recycle_latency: 39510802Srene.dejong@arm.com self.recycle_latency = options.recycle_latency 39610802Srene.dejong@arm.com 39710802Srene.dejong@arm.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 39810802Srene.dejong@arm.com req_to_l3, probe_to_l3, resp_to_l3): 39910802Srene.dejong@arm.com self.reqToDir = req_to_dir 40010802Srene.dejong@arm.com self.respToDir = resp_to_dir 40110802Srene.dejong@arm.com self.l3UnblockToDir = l3_unblock_to_dir 40210802Srene.dejong@arm.com self.reqToL3 = req_to_l3 40310802Srene.dejong@arm.com self.probeToL3 = probe_to_l3 40410802Srene.dejong@arm.com self.respToL3 = resp_to_l3 40510802Srene.dejong@arm.com 40610802Srene.dejong@arm.com 40710802Srene.dejong@arm.com 40810802Srene.dejong@arm.comdef define_options(parser): 40910802Srene.dejong@arm.com parser.add_option("--num-subcaches", type="int", default=4) 41010802Srene.dejong@arm.com parser.add_option("--l3-data-latency", type="int", default=20) 41110802Srene.dejong@arm.com parser.add_option("--l3-tag-latency", type="int", default=15) 41210802Srene.dejong@arm.com parser.add_option("--cpu-to-dir-latency", type="int", default=15) 41310802Srene.dejong@arm.com parser.add_option("--gpu-to-dir-latency", type="int", default=160) 41410802Srene.dejong@arm.com parser.add_option("--no-resource-stalls", action="store_false", 41510802Srene.dejong@arm.com default=True) 41610802Srene.dejong@arm.com parser.add_option("--num-tbes", type="int", default=256) 41710802Srene.dejong@arm.com parser.add_option("--l2-latency", type="int", default=50) # load to use 41810802Srene.dejong@arm.com parser.add_option("--num-tccs", type="int", default=1, 41910802Srene.dejong@arm.com help="number of TCC directories and banks in the GPU") 42010802Srene.dejong@arm.com parser.add_option("--TCP_latency", type="int", default=4, 42110802Srene.dejong@arm.com help="TCP latency") 42210802Srene.dejong@arm.com parser.add_option("--TCC_latency", type="int", default=16, 42310802Srene.dejong@arm.com help="TCC latency") 42410802Srene.dejong@arm.com parser.add_option("--tcc-size", type='string', default='256kB', 42510802Srene.dejong@arm.com help="agregate tcc size") 42610802Srene.dejong@arm.com parser.add_option("--tcp-size", type='string', default='16kB', 42710802Srene.dejong@arm.com help="tcp size") 42810802Srene.dejong@arm.com parser.add_option("--tcc-dir-factor", type='int', default=4, 42910802Srene.dejong@arm.com help="TCCdir size = factor *(TCPs + TCC)") 43010802Srene.dejong@arm.com 43110802Srene.dejong@arm.comdef create_system(options, full_system, system, dma_devices, bootmem, 43210802Srene.dejong@arm.com ruby_system): 43310802Srene.dejong@arm.com if buildEnv['PROTOCOL'] != 'GPU_RfO': 43410802Srene.dejong@arm.com panic("This script requires the GPU_RfO protocol to be built.") 43510802Srene.dejong@arm.com 43610802Srene.dejong@arm.com cpu_sequencers = [] 43710802Srene.dejong@arm.com 43810802Srene.dejong@arm.com # 43910802Srene.dejong@arm.com # The ruby network creation expects the list of nodes in the system to be 44010802Srene.dejong@arm.com # consistent with the NetDest list. Therefore the l1 controller nodes 44110802Srene.dejong@arm.com # must be listed before the directory nodes and directory nodes before 44210802Srene.dejong@arm.com # dma nodes, etc. 44310802Srene.dejong@arm.com # 44410802Srene.dejong@arm.com cp_cntrl_nodes = [] 44510802Srene.dejong@arm.com tcp_cntrl_nodes = [] 44610802Srene.dejong@arm.com sqc_cntrl_nodes = [] 44710802Srene.dejong@arm.com tcc_cntrl_nodes = [] 44810802Srene.dejong@arm.com tccdir_cntrl_nodes = [] 44910802Srene.dejong@arm.com dir_cntrl_nodes = [] 45010802Srene.dejong@arm.com l3_cntrl_nodes = [] 45110802Srene.dejong@arm.com 45210802Srene.dejong@arm.com # 45310802Srene.dejong@arm.com # Must create the individual controllers before the network to ensure the 45410802Srene.dejong@arm.com # controller constructors are called before the network constructor 45510802Srene.dejong@arm.com # 45610802Srene.dejong@arm.com 45710802Srene.dejong@arm.com TCC_bits = int(math.log(options.num_tccs, 2)) 45810802Srene.dejong@arm.com 45910802Srene.dejong@arm.com # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 46010802Srene.dejong@arm.com # Clusters 46110802Srene.dejong@arm.com mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 46210802Srene.dejong@arm.com 46310802Srene.dejong@arm.com if options.numa_high_bit: 46410802Srene.dejong@arm.com numa_bit = options.numa_high_bit 46510802Srene.dejong@arm.com else: 46610802Srene.dejong@arm.com # if the numa_bit is not specified, set the directory bits as the 46710802Srene.dejong@arm.com # lowest bits above the block offset bits, and the numa_bit as the 46810802Srene.dejong@arm.com # highest of those directory bits 46910802Srene.dejong@arm.com dir_bits = int(math.log(options.num_dirs, 2)) 47010802Srene.dejong@arm.com block_size_bits = int(math.log(options.cacheline_size, 2)) 47110802Srene.dejong@arm.com numa_bit = block_size_bits + dir_bits - 1 47210802Srene.dejong@arm.com 47310802Srene.dejong@arm.com for i in range(options.num_dirs): 47410802Srene.dejong@arm.com dir_ranges = [] 47510802Srene.dejong@arm.com for r in system.mem_ranges: 47610802Srene.dejong@arm.com addr_range = m5.objects.AddrRange(r.start, size = r.size(), 47710802Srene.dejong@arm.com intlvHighBit = numa_bit, 47810802Srene.dejong@arm.com intlvBits = dir_bits, 47910802Srene.dejong@arm.com intlvMatch = i) 48010802Srene.dejong@arm.com dir_ranges.append(addr_range) 48110802Srene.dejong@arm.com 48210802Srene.dejong@arm.com dir_cntrl = DirCntrl(TCC_select_num_bits = TCC_bits) 48310802Srene.dejong@arm.com dir_cntrl.create(options, dir_ranges, ruby_system, system) 48410802Srene.dejong@arm.com dir_cntrl.number_of_TBEs = 2560 * options.num_compute_units 48510802Srene.dejong@arm.com #Enough TBEs for all TCP TBEs 48610802Srene.dejong@arm.com 48710802Srene.dejong@arm.com # Connect the Directory controller to the ruby network 48810802Srene.dejong@arm.com dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 48910802Srene.dejong@arm.com dir_cntrl.requestFromCores.slave = ruby_system.network.master 49010802Srene.dejong@arm.com 49110802Srene.dejong@arm.com dir_cntrl.responseFromCores = MessageBuffer() 49210802Srene.dejong@arm.com dir_cntrl.responseFromCores.slave = ruby_system.network.master 49310802Srene.dejong@arm.com 49410802Srene.dejong@arm.com dir_cntrl.unblockFromCores = MessageBuffer() 49510802Srene.dejong@arm.com dir_cntrl.unblockFromCores.slave = ruby_system.network.master 49610802Srene.dejong@arm.com 49710802Srene.dejong@arm.com dir_cntrl.probeToCore = MessageBuffer() 49810802Srene.dejong@arm.com dir_cntrl.probeToCore.master = ruby_system.network.slave 49910802Srene.dejong@arm.com 50010802Srene.dejong@arm.com dir_cntrl.responseToCore = MessageBuffer() 50110802Srene.dejong@arm.com dir_cntrl.responseToCore.master = ruby_system.network.slave 50210802Srene.dejong@arm.com 50310802Srene.dejong@arm.com dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 50410802Srene.dejong@arm.com dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 50510802Srene.dejong@arm.com dir_cntrl.responseFromMemory = MessageBuffer() 50610802Srene.dejong@arm.com 50710802Srene.dejong@arm.com exec("system.dir_cntrl%d = dir_cntrl" % i) 50810802Srene.dejong@arm.com dir_cntrl_nodes.append(dir_cntrl) 50910802Srene.dejong@arm.com 51010802Srene.dejong@arm.com mainCluster.add(dir_cntrl) 51110802Srene.dejong@arm.com 51210802Srene.dejong@arm.com # For an odd number of CPUs, still create the right number of controllers 51310802Srene.dejong@arm.com cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 51410802Srene.dejong@arm.com for i in range((options.num_cpus + 1) // 2): 51510802Srene.dejong@arm.com 51610802Srene.dejong@arm.com cp_cntrl = CPCntrl() 51710802Srene.dejong@arm.com cp_cntrl.create(options, ruby_system, system) 51810802Srene.dejong@arm.com 51910802Srene.dejong@arm.com exec("system.cp_cntrl%d = cp_cntrl" % i) 52010802Srene.dejong@arm.com # 52110802Srene.dejong@arm.com # Add controllers and sequencers to the appropriate lists 52210802Srene.dejong@arm.com # 52310802Srene.dejong@arm.com cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 52410802Srene.dejong@arm.com 52510802Srene.dejong@arm.com # Connect the CP controllers and the network 52610802Srene.dejong@arm.com cp_cntrl.requestFromCore = MessageBuffer() 52710802Srene.dejong@arm.com cp_cntrl.requestFromCore.master = ruby_system.network.slave 52810802Srene.dejong@arm.com 52910802Srene.dejong@arm.com cp_cntrl.responseFromCore = MessageBuffer() 53010802Srene.dejong@arm.com cp_cntrl.responseFromCore.master = ruby_system.network.slave 53110802Srene.dejong@arm.com 53210802Srene.dejong@arm.com cp_cntrl.unblockFromCore = MessageBuffer() 53310802Srene.dejong@arm.com cp_cntrl.unblockFromCore.master = ruby_system.network.slave 53410802Srene.dejong@arm.com 53510802Srene.dejong@arm.com cp_cntrl.probeToCore = MessageBuffer() 53610802Srene.dejong@arm.com cp_cntrl.probeToCore.slave = ruby_system.network.master 53710802Srene.dejong@arm.com 53810802Srene.dejong@arm.com cp_cntrl.responseToCore = MessageBuffer() 53910802Srene.dejong@arm.com cp_cntrl.responseToCore.slave = ruby_system.network.master 54010802Srene.dejong@arm.com 54110802Srene.dejong@arm.com cp_cntrl.mandatoryQueue = MessageBuffer() 54210802Srene.dejong@arm.com cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 54310802Srene.dejong@arm.com 54410802Srene.dejong@arm.com cpuCluster.add(cp_cntrl) 54510802Srene.dejong@arm.com 54610802Srene.dejong@arm.com gpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 54710802Srene.dejong@arm.com 54810802Srene.dejong@arm.com for i in range(options.num_compute_units): 54910802Srene.dejong@arm.com 55010802Srene.dejong@arm.com tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 55110802Srene.dejong@arm.com number_of_TBEs = 2560) # max outstanding requests 55210802Srene.dejong@arm.com tcp_cntrl.create(options, ruby_system, system) 55310802Srene.dejong@arm.com 55410802Srene.dejong@arm.com exec("system.tcp_cntrl%d = tcp_cntrl" % i) 55510802Srene.dejong@arm.com # 55610802Srene.dejong@arm.com # Add controllers and sequencers to the appropriate lists 55710802Srene.dejong@arm.com # 55810802Srene.dejong@arm.com cpu_sequencers.append(tcp_cntrl.coalescer) 55910802Srene.dejong@arm.com tcp_cntrl_nodes.append(tcp_cntrl) 56010802Srene.dejong@arm.com 56110802Srene.dejong@arm.com # Connect the TCP controller to the ruby network 56210802Srene.dejong@arm.com tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 56310802Srene.dejong@arm.com tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 56410802Srene.dejong@arm.com 56510802Srene.dejong@arm.com tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 56610802Srene.dejong@arm.com tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 56710802Srene.dejong@arm.com 56810802Srene.dejong@arm.com tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True) 56910802Srene.dejong@arm.com tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 57010802Srene.dejong@arm.com 57110802Srene.dejong@arm.com tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 57210802Srene.dejong@arm.com tcp_cntrl.probeToTCP.slave = ruby_system.network.master 57310802Srene.dejong@arm.com 57410802Srene.dejong@arm.com tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 57510802Srene.dejong@arm.com tcp_cntrl.responseToTCP.slave = ruby_system.network.master 57610802Srene.dejong@arm.com 57710802Srene.dejong@arm.com tcp_cntrl.mandatoryQueue = MessageBuffer() 57810802Srene.dejong@arm.com 57910802Srene.dejong@arm.com gpuCluster.add(tcp_cntrl) 58010802Srene.dejong@arm.com 58110802Srene.dejong@arm.com for i in range(options.num_sqc): 58210802Srene.dejong@arm.com 58310802Srene.dejong@arm.com sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 58410802Srene.dejong@arm.com sqc_cntrl.create(options, ruby_system, system) 58510802Srene.dejong@arm.com 58610802Srene.dejong@arm.com exec("system.sqc_cntrl%d = sqc_cntrl" % i) 58710802Srene.dejong@arm.com # 58810802Srene.dejong@arm.com # Add controllers and sequencers to the appropriate lists 58910802Srene.dejong@arm.com # 59010802Srene.dejong@arm.com cpu_sequencers.append(sqc_cntrl.sequencer) 59110802Srene.dejong@arm.com 59210802Srene.dejong@arm.com # Connect the SQC controller to the ruby network 59310802Srene.dejong@arm.com sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 59410802Srene.dejong@arm.com sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 59510802Srene.dejong@arm.com 59610802Srene.dejong@arm.com sqc_cntrl.responseFromSQC = MessageBuffer(ordered = True) 59710802Srene.dejong@arm.com sqc_cntrl.responseFromSQC.master = ruby_system.network.slave 59810802Srene.dejong@arm.com 59910802Srene.dejong@arm.com sqc_cntrl.unblockFromCore = MessageBuffer(ordered = True) 60010802Srene.dejong@arm.com sqc_cntrl.unblockFromCore.master = ruby_system.network.slave 60110802Srene.dejong@arm.com 60210802Srene.dejong@arm.com sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 60310802Srene.dejong@arm.com sqc_cntrl.probeToSQC.slave = ruby_system.network.master 60410802Srene.dejong@arm.com 60510802Srene.dejong@arm.com sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 60610802Srene.dejong@arm.com sqc_cntrl.responseToSQC.slave = ruby_system.network.master 60710802Srene.dejong@arm.com 60810802Srene.dejong@arm.com sqc_cntrl.mandatoryQueue = MessageBuffer() 60910802Srene.dejong@arm.com 61010802Srene.dejong@arm.com # SQC also in GPU cluster 61110802Srene.dejong@arm.com gpuCluster.add(sqc_cntrl) 61210802Srene.dejong@arm.com 61310802Srene.dejong@arm.com for i in range(options.num_cp): 61410802Srene.dejong@arm.com 61510802Srene.dejong@arm.com tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 61610802Srene.dejong@arm.com number_of_TBEs = 2560) # max outstanding requests 61710802Srene.dejong@arm.com tcp_cntrl.createCP(options, ruby_system, system) 61810802Srene.dejong@arm.com 61910802Srene.dejong@arm.com exec("system.tcp_cntrl%d = tcp_cntrl" % (options.num_compute_units + i)) 62010802Srene.dejong@arm.com # 62110802Srene.dejong@arm.com # Add controllers and sequencers to the appropriate lists 62210802Srene.dejong@arm.com # 62310802Srene.dejong@arm.com cpu_sequencers.append(tcp_cntrl.sequencer) 62410802Srene.dejong@arm.com tcp_cntrl_nodes.append(tcp_cntrl) 62510802Srene.dejong@arm.com 62610802Srene.dejong@arm.com # Connect the TCP controller to the ruby network 62710802Srene.dejong@arm.com tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 62810802Srene.dejong@arm.com tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 62910802Srene.dejong@arm.com 63010802Srene.dejong@arm.com tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 63110802Srene.dejong@arm.com tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 63210802Srene.dejong@arm.com 63310802Srene.dejong@arm.com tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True) 63410802Srene.dejong@arm.com tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 63510802Srene.dejong@arm.com 63610802Srene.dejong@arm.com tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 63710802Srene.dejong@arm.com tcp_cntrl.probeToTCP.slave = ruby_system.network.master 63810802Srene.dejong@arm.com 63910802Srene.dejong@arm.com tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 64010802Srene.dejong@arm.com tcp_cntrl.responseToTCP.slave = ruby_system.network.master 64110802Srene.dejong@arm.com 64210802Srene.dejong@arm.com tcp_cntrl.mandatoryQueue = MessageBuffer() 64310802Srene.dejong@arm.com 64410802Srene.dejong@arm.com gpuCluster.add(tcp_cntrl) 64510802Srene.dejong@arm.com 64610802Srene.dejong@arm.com sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 64710802Srene.dejong@arm.com sqc_cntrl.createCP(options, ruby_system, system) 64810802Srene.dejong@arm.com 64910802Srene.dejong@arm.com exec("system.sqc_cntrl%d = sqc_cntrl" % (options.num_compute_units + i)) 65010802Srene.dejong@arm.com # 65110802Srene.dejong@arm.com # Add controllers and sequencers to the appropriate lists 65210802Srene.dejong@arm.com # 65310802Srene.dejong@arm.com cpu_sequencers.append(sqc_cntrl.sequencer) 65410802Srene.dejong@arm.com 65510802Srene.dejong@arm.com # Connect the SQC controller to the ruby network 65610802Srene.dejong@arm.com sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 65710802Srene.dejong@arm.com sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 65810802Srene.dejong@arm.com 65910802Srene.dejong@arm.com sqc_cntrl.responseFromSQC = MessageBuffer(ordered = True) 66010802Srene.dejong@arm.com sqc_cntrl.responseFromSQC.master = ruby_system.network.slave 66110802Srene.dejong@arm.com 66210802Srene.dejong@arm.com sqc_cntrl.unblockFromCore = MessageBuffer(ordered = True) 66310802Srene.dejong@arm.com sqc_cntrl.unblockFromCore.master = ruby_system.network.slave 66410802Srene.dejong@arm.com 66510802Srene.dejong@arm.com sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 66610802Srene.dejong@arm.com sqc_cntrl.probeToSQC.slave = ruby_system.network.master 66710802Srene.dejong@arm.com 66810802Srene.dejong@arm.com sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 66910802Srene.dejong@arm.com sqc_cntrl.responseToSQC.slave = ruby_system.network.master 67010802Srene.dejong@arm.com 67110802Srene.dejong@arm.com sqc_cntrl.mandatoryQueue = MessageBuffer() 67210802Srene.dejong@arm.com 67310802Srene.dejong@arm.com # SQC also in GPU cluster 67410802Srene.dejong@arm.com gpuCluster.add(sqc_cntrl) 67510802Srene.dejong@arm.com 67610802Srene.dejong@arm.com for i in range(options.num_tccs): 67710802Srene.dejong@arm.com 67810802Srene.dejong@arm.com tcc_cntrl = TCCCntrl(TCC_select_num_bits = TCC_bits, 67910802Srene.dejong@arm.com number_of_TBEs = options.num_compute_units * 2560) 68010802Srene.dejong@arm.com #Enough TBEs for all TCP TBEs 68110802Srene.dejong@arm.com tcc_cntrl.create(options, ruby_system, system) 68210802Srene.dejong@arm.com tcc_cntrl_nodes.append(tcc_cntrl) 68310802Srene.dejong@arm.com 68410802Srene.dejong@arm.com tccdir_cntrl = TCCDirCntrl(TCC_select_num_bits = TCC_bits, 68510802Srene.dejong@arm.com number_of_TBEs = options.num_compute_units * 2560) 68610802Srene.dejong@arm.com #Enough TBEs for all TCP TBEs 68710802Srene.dejong@arm.com tccdir_cntrl.create(options, ruby_system, system) 68810802Srene.dejong@arm.com tccdir_cntrl_nodes.append(tccdir_cntrl) 68910802Srene.dejong@arm.com 69010802Srene.dejong@arm.com exec("system.tcc_cntrl%d = tcc_cntrl" % i) 69110802Srene.dejong@arm.com exec("system.tccdir_cntrl%d = tccdir_cntrl" % i) 69210802Srene.dejong@arm.com 69310802Srene.dejong@arm.com # connect all of the wire buffers between L3 and dirs up 69410802Srene.dejong@arm.com req_to_tccdir = RubyWireBuffer() 69510802Srene.dejong@arm.com resp_to_tccdir = RubyWireBuffer() 69610802Srene.dejong@arm.com tcc_unblock_to_tccdir = RubyWireBuffer() 69710802Srene.dejong@arm.com req_to_tcc = RubyWireBuffer() 69810802Srene.dejong@arm.com probe_to_tcc = RubyWireBuffer() 69910802Srene.dejong@arm.com resp_to_tcc = RubyWireBuffer() 70010802Srene.dejong@arm.com 70110802Srene.dejong@arm.com tcc_cntrl.connectWireBuffers(req_to_tccdir, resp_to_tccdir, 70210802Srene.dejong@arm.com tcc_unblock_to_tccdir, req_to_tcc, 70310802Srene.dejong@arm.com probe_to_tcc, resp_to_tcc) 70410802Srene.dejong@arm.com tccdir_cntrl.connectWireBuffers(req_to_tccdir, resp_to_tccdir, 70510802Srene.dejong@arm.com tcc_unblock_to_tccdir, req_to_tcc, 70610802Srene.dejong@arm.com probe_to_tcc, resp_to_tcc) 70710802Srene.dejong@arm.com 70810802Srene.dejong@arm.com # Connect the TCC controller to the ruby network 70910802Srene.dejong@arm.com tcc_cntrl.responseFromTCC = MessageBuffer(ordered = True) 71010802Srene.dejong@arm.com tcc_cntrl.responseFromTCC.master = ruby_system.network.slave 71110802Srene.dejong@arm.com 71210802Srene.dejong@arm.com tcc_cntrl.responseToTCC = MessageBuffer(ordered = True) 71310802Srene.dejong@arm.com tcc_cntrl.responseToTCC.slave = ruby_system.network.master 71410802Srene.dejong@arm.com 71510802Srene.dejong@arm.com # Connect the TCC Dir controller to the ruby network 71610802Srene.dejong@arm.com tccdir_cntrl.requestFromTCP = MessageBuffer(ordered = True) 71710802Srene.dejong@arm.com tccdir_cntrl.requestFromTCP.slave = ruby_system.network.master 71810802Srene.dejong@arm.com 71910802Srene.dejong@arm.com tccdir_cntrl.responseFromTCP = MessageBuffer(ordered = True) 72010802Srene.dejong@arm.com tccdir_cntrl.responseFromTCP.slave = ruby_system.network.master 72110802Srene.dejong@arm.com 72210802Srene.dejong@arm.com tccdir_cntrl.unblockFromTCP = MessageBuffer(ordered = True) 72310802Srene.dejong@arm.com tccdir_cntrl.unblockFromTCP.slave = ruby_system.network.master 72410802Srene.dejong@arm.com 72510802Srene.dejong@arm.com tccdir_cntrl.probeToCore = MessageBuffer(ordered = True) 72610802Srene.dejong@arm.com tccdir_cntrl.probeToCore.master = ruby_system.network.slave 72710802Srene.dejong@arm.com 72810802Srene.dejong@arm.com tccdir_cntrl.responseToCore = MessageBuffer(ordered = True) 72910802Srene.dejong@arm.com tccdir_cntrl.responseToCore.master = ruby_system.network.slave 73010802Srene.dejong@arm.com 73110802Srene.dejong@arm.com tccdir_cntrl.probeFromNB = MessageBuffer() 73210802Srene.dejong@arm.com tccdir_cntrl.probeFromNB.slave = ruby_system.network.master 73310802Srene.dejong@arm.com 73410802Srene.dejong@arm.com tccdir_cntrl.responseFromNB = MessageBuffer() 73510802Srene.dejong@arm.com tccdir_cntrl.responseFromNB.slave = ruby_system.network.master 73610802Srene.dejong@arm.com 73710802Srene.dejong@arm.com tccdir_cntrl.requestToNB = MessageBuffer() 73810802Srene.dejong@arm.com tccdir_cntrl.requestToNB.master = ruby_system.network.slave 73910802Srene.dejong@arm.com 74010802Srene.dejong@arm.com tccdir_cntrl.responseToNB = MessageBuffer() 74110802Srene.dejong@arm.com tccdir_cntrl.responseToNB.master = ruby_system.network.slave 74210802Srene.dejong@arm.com 74310802Srene.dejong@arm.com tccdir_cntrl.unblockToNB = MessageBuffer() 74410802Srene.dejong@arm.com tccdir_cntrl.unblockToNB.master = ruby_system.network.slave 74510802Srene.dejong@arm.com 74610802Srene.dejong@arm.com tccdir_cntrl.triggerQueue = MessageBuffer(ordered = True) 74710802Srene.dejong@arm.com 74810802Srene.dejong@arm.com # TCC cntrls added to the GPU cluster 74910802Srene.dejong@arm.com gpuCluster.add(tcc_cntrl) 75010802Srene.dejong@arm.com gpuCluster.add(tccdir_cntrl) 75110802Srene.dejong@arm.com 75210802Srene.dejong@arm.com # Assuming no DMA devices 75310802Srene.dejong@arm.com assert(len(dma_devices) == 0) 75410802Srene.dejong@arm.com 75510802Srene.dejong@arm.com # Add cpu/gpu clusters to main cluster 75610802Srene.dejong@arm.com mainCluster.add(cpuCluster) 75710802Srene.dejong@arm.com mainCluster.add(gpuCluster) 75810802Srene.dejong@arm.com 75910802Srene.dejong@arm.com ruby_system.network.number_of_virtual_networks = 10 76010802Srene.dejong@arm.com 76110802Srene.dejong@arm.com return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 76210802Srene.dejong@arm.com