GPU_RfO.py revision 11670
17405SAli.Saidi@ARM.com# 211573SDylan.Johnson@ARM.com# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 37405SAli.Saidi@ARM.com# All rights reserved. 47405SAli.Saidi@ARM.com# 57405SAli.Saidi@ARM.com# For use for simulation and test purposes only 67405SAli.Saidi@ARM.com# 77405SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 87405SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are met: 97405SAli.Saidi@ARM.com# 107405SAli.Saidi@ARM.com# 1. Redistributions of source code must retain the above copyright notice, 117405SAli.Saidi@ARM.com# this list of conditions and the following disclaimer. 127405SAli.Saidi@ARM.com# 137405SAli.Saidi@ARM.com# 2. Redistributions in binary form must reproduce the above copyright notice, 147405SAli.Saidi@ARM.com# this list of conditions and the following disclaimer in the documentation 157405SAli.Saidi@ARM.com# and/or other materials provided with the distribution. 167405SAli.Saidi@ARM.com# 177405SAli.Saidi@ARM.com# 3. Neither the name of the copyright holder nor the names of its contributors 187405SAli.Saidi@ARM.com# may be used to endorse or promote products derived from this software 197405SAli.Saidi@ARM.com# without specific prior written permission. 207405SAli.Saidi@ARM.com# 217405SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 227405SAli.Saidi@ARM.com# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 237405SAli.Saidi@ARM.com# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 247405SAli.Saidi@ARM.com# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 257405SAli.Saidi@ARM.com# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 267405SAli.Saidi@ARM.com# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 277405SAli.Saidi@ARM.com# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 287405SAli.Saidi@ARM.com# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 297405SAli.Saidi@ARM.com# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 307405SAli.Saidi@ARM.com# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 317405SAli.Saidi@ARM.com# POSSIBILITY OF SUCH DAMAGE. 327405SAli.Saidi@ARM.com# 337405SAli.Saidi@ARM.com# Author: Lisa Hsu 347405SAli.Saidi@ARM.com# 357405SAli.Saidi@ARM.com 367405SAli.Saidi@ARM.comimport math 377405SAli.Saidi@ARM.comimport m5 387405SAli.Saidi@ARM.comfrom m5.objects import * 397405SAli.Saidi@ARM.comfrom m5.defines import buildEnv 407405SAli.Saidi@ARM.comfrom Ruby import create_topology 417405SAli.Saidi@ARM.comfrom Ruby import send_evicts 4210461SAndreas.Sandberg@ARM.com 439050Schander.sudanthi@arm.comfrom topologies.Cluster import Cluster 448887Sgeoffrey.blake@arm.comfrom topologies.Crossbar import Crossbar 4510461SAndreas.Sandberg@ARM.com 468232Snate@binkert.orgclass CntrlBase: 478232Snate@binkert.org _seqs = 0 4810844Sandreas.sandberg@arm.com @classmethod 499384SAndreas.Sandberg@arm.com def seqCount(cls): 507678Sgblack@eecs.umich.edu # Use SeqCount not class since we need global count 518059SAli.Saidi@ARM.com CntrlBase._seqs += 1 528284SAli.Saidi@ARM.com return CntrlBase._seqs - 1 537405SAli.Saidi@ARM.com 547405SAli.Saidi@ARM.com _cntrls = 0 557405SAli.Saidi@ARM.com @classmethod 567405SAli.Saidi@ARM.com def cntrlCount(cls): 5710037SARM gem5 Developers # Use CntlCount not class since we need global count 5810037SARM gem5 Developers CntrlBase._cntrls += 1 5911768SCurtis.Dunham@arm.com return CntrlBase._cntrls - 1 6010037SARM gem5 Developers 6110037SARM gem5 Developers _version = 0 6210037SARM gem5 Developers @classmethod 6310037SARM gem5 Developers def versionCount(cls): 6411768SCurtis.Dunham@arm.com cls._version += 1 # Use count for this particular type 6510037SARM gem5 Developers return cls._version - 1 6610037SARM gem5 Developers 6711768SCurtis.Dunham@arm.comclass TccDirCache(RubyCache): 6811768SCurtis.Dunham@arm.com size = "512kB" 6911768SCurtis.Dunham@arm.com assoc = 16 7011768SCurtis.Dunham@arm.com resourceStalls = False 7111768SCurtis.Dunham@arm.com def create(self, options): 7211768SCurtis.Dunham@arm.com self.size = MemorySize(options.tcc_size) 7311768SCurtis.Dunham@arm.com self.size.value += (options.num_compute_units * 7411768SCurtis.Dunham@arm.com (MemorySize(options.tcp_size).value) * 7511768SCurtis.Dunham@arm.com options.tcc_dir_factor) / long(options.num_tccs) 7611768SCurtis.Dunham@arm.com self.start_index_bit = math.log(options.cacheline_size, 2) + \ 7711768SCurtis.Dunham@arm.com math.log(options.num_tccs, 2) 7811768SCurtis.Dunham@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 7910037SARM gem5 Developers 8010037SARM gem5 Developersclass L1DCache(RubyCache): 8110037SARM gem5 Developers resourceStalls = False 8211768SCurtis.Dunham@arm.com def create(self, options): 8311768SCurtis.Dunham@arm.com self.size = MemorySize(options.l1d_size) 8411768SCurtis.Dunham@arm.com self.assoc = options.l1d_assoc 8511768SCurtis.Dunham@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 8611768SCurtis.Dunham@arm.com 8711768SCurtis.Dunham@arm.comclass L1ICache(RubyCache): 8811768SCurtis.Dunham@arm.com resourceStalls = False 8911768SCurtis.Dunham@arm.com def create(self, options): 9010037SARM gem5 Developers self.size = MemorySize(options.l1i_size) 9111768SCurtis.Dunham@arm.com self.assoc = options.l1i_assoc 9211768SCurtis.Dunham@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 9311768SCurtis.Dunham@arm.com 9411768SCurtis.Dunham@arm.comclass L2Cache(RubyCache): 9510037SARM gem5 Developers resourceStalls = False 9611768SCurtis.Dunham@arm.com def create(self, options): 9711768SCurtis.Dunham@arm.com self.size = MemorySize(options.l2_size) 9811768SCurtis.Dunham@arm.com self.assoc = options.l2_assoc 9911768SCurtis.Dunham@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 10011768SCurtis.Dunham@arm.com 10111768SCurtis.Dunham@arm.com 10211768SCurtis.Dunham@arm.comclass CPCntrl(CorePair_Controller, CntrlBase): 10311768SCurtis.Dunham@arm.com 10411768SCurtis.Dunham@arm.com def create(self, options, ruby_system, system): 10511768SCurtis.Dunham@arm.com self.version = self.versionCount() 10611768SCurtis.Dunham@arm.com 10711768SCurtis.Dunham@arm.com self.L1Icache = L1ICache() 10811768SCurtis.Dunham@arm.com self.L1Icache.create(options) 10911768SCurtis.Dunham@arm.com self.L1D0cache = L1DCache() 11011768SCurtis.Dunham@arm.com self.L1D0cache.create(options) 11111768SCurtis.Dunham@arm.com self.L1D1cache = L1DCache() 11211768SCurtis.Dunham@arm.com self.L1D1cache.create(options) 11311768SCurtis.Dunham@arm.com self.L2cache = L2Cache() 11410037SARM gem5 Developers self.L2cache.create(options) 11511768SCurtis.Dunham@arm.com 11611768SCurtis.Dunham@arm.com self.sequencer = RubySequencer() 11711768SCurtis.Dunham@arm.com self.sequencer.icache_hit_latency = 2 11811768SCurtis.Dunham@arm.com self.sequencer.dcache_hit_latency = 2 11910037SARM gem5 Developers self.sequencer.version = self.seqCount() 12011768SCurtis.Dunham@arm.com self.sequencer.icache = self.L1Icache 12111768SCurtis.Dunham@arm.com self.sequencer.dcache = self.L1D0cache 12211768SCurtis.Dunham@arm.com self.sequencer.ruby_system = ruby_system 12311768SCurtis.Dunham@arm.com self.sequencer.coreid = 0 12411768SCurtis.Dunham@arm.com self.sequencer.is_cpu_sequencer = True 12511768SCurtis.Dunham@arm.com 12610037SARM gem5 Developers self.sequencer1 = RubySequencer() 12711768SCurtis.Dunham@arm.com self.sequencer1.version = self.seqCount() 12811768SCurtis.Dunham@arm.com self.sequencer1.icache = self.L1Icache 12911768SCurtis.Dunham@arm.com self.sequencer1.dcache = self.L1D1cache 13011768SCurtis.Dunham@arm.com self.sequencer1.icache_hit_latency = 2 13111768SCurtis.Dunham@arm.com self.sequencer1.dcache_hit_latency = 2 13211768SCurtis.Dunham@arm.com self.sequencer1.ruby_system = ruby_system 13311768SCurtis.Dunham@arm.com self.sequencer1.coreid = 1 13411768SCurtis.Dunham@arm.com self.sequencer1.is_cpu_sequencer = True 13511768SCurtis.Dunham@arm.com 13611768SCurtis.Dunham@arm.com self.issue_latency = options.cpu_to_dir_latency 13711768SCurtis.Dunham@arm.com self.send_evictions = send_evicts(options) 13811768SCurtis.Dunham@arm.com 13911768SCurtis.Dunham@arm.com self.ruby_system = ruby_system 14011768SCurtis.Dunham@arm.com 14111768SCurtis.Dunham@arm.com if options.recycle_latency: 14211768SCurtis.Dunham@arm.com self.recycle_latency = options.recycle_latency 14311768SCurtis.Dunham@arm.com 14411768SCurtis.Dunham@arm.comclass TCPCache(RubyCache): 14511768SCurtis.Dunham@arm.com assoc = 8 14611768SCurtis.Dunham@arm.com dataArrayBanks = 16 14711768SCurtis.Dunham@arm.com tagArrayBanks = 4 14811768SCurtis.Dunham@arm.com dataAccessLatency = 4 14911768SCurtis.Dunham@arm.com tagAccessLatency = 1 15011768SCurtis.Dunham@arm.com def create(self, options): 15111768SCurtis.Dunham@arm.com self.size = MemorySize(options.tcp_size) 15211768SCurtis.Dunham@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 15311768SCurtis.Dunham@arm.com 15411768SCurtis.Dunham@arm.comclass TCPCntrl(TCP_Controller, CntrlBase): 15511768SCurtis.Dunham@arm.com 15611768SCurtis.Dunham@arm.com def create(self, options, ruby_system, system): 15711768SCurtis.Dunham@arm.com self.version = self.versionCount() 15811768SCurtis.Dunham@arm.com 15911768SCurtis.Dunham@arm.com self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency) 16011768SCurtis.Dunham@arm.com self.L1cache.resourceStalls = options.no_resource_stalls 16111768SCurtis.Dunham@arm.com self.L1cache.create(options) 16211768SCurtis.Dunham@arm.com 16311768SCurtis.Dunham@arm.com self.coalescer = RubyGPUCoalescer() 16411768SCurtis.Dunham@arm.com self.coalescer.version = self.seqCount() 16511768SCurtis.Dunham@arm.com self.coalescer.icache = self.L1cache 16611768SCurtis.Dunham@arm.com self.coalescer.dcache = self.L1cache 16711768SCurtis.Dunham@arm.com self.coalescer.ruby_system = ruby_system 16811768SCurtis.Dunham@arm.com self.coalescer.support_inst_reqs = False 16911768SCurtis.Dunham@arm.com self.coalescer.is_cpu_sequencer = False 17011768SCurtis.Dunham@arm.com self.coalescer.max_outstanding_requests = options.simds_per_cu * \ 17111768SCurtis.Dunham@arm.com options.wfs_per_simd * \ 17211768SCurtis.Dunham@arm.com options.wf_size 17311768SCurtis.Dunham@arm.com 17411768SCurtis.Dunham@arm.com self.sequencer = RubySequencer() 17511768SCurtis.Dunham@arm.com self.sequencer.version = self.seqCount() 17611768SCurtis.Dunham@arm.com self.sequencer.icache = self.L1cache 17711768SCurtis.Dunham@arm.com self.sequencer.dcache = self.L1cache 17811768SCurtis.Dunham@arm.com self.sequencer.ruby_system = ruby_system 17911768SCurtis.Dunham@arm.com self.sequencer.is_cpu_sequencer = True 18011768SCurtis.Dunham@arm.com 18111768SCurtis.Dunham@arm.com self.use_seq_not_coal = False 18211768SCurtis.Dunham@arm.com 18311768SCurtis.Dunham@arm.com self.ruby_system = ruby_system 18411768SCurtis.Dunham@arm.com 18511768SCurtis.Dunham@arm.com if options.recycle_latency: 18611768SCurtis.Dunham@arm.com self.recycle_latency = options.recycle_latency 18711768SCurtis.Dunham@arm.com 18811768SCurtis.Dunham@arm.com def createCP(self, options, ruby_system, system): 18911768SCurtis.Dunham@arm.com self.version = self.versionCount() 19011768SCurtis.Dunham@arm.com 19111768SCurtis.Dunham@arm.com self.L1cache = TCPCache(tagAccessLatency = options.TCP_latency) 19211768SCurtis.Dunham@arm.com self.L1cache.resourceStalls = options.no_resource_stalls 19311768SCurtis.Dunham@arm.com self.L1cache.create(options) 19411768SCurtis.Dunham@arm.com 19511768SCurtis.Dunham@arm.com self.coalescer = RubyGPUCoalescer() 19611768SCurtis.Dunham@arm.com self.coalescer.version = self.seqCount() 19711768SCurtis.Dunham@arm.com self.coalescer.icache = self.L1cache 19811768SCurtis.Dunham@arm.com self.coalescer.dcache = self.L1cache 19911768SCurtis.Dunham@arm.com self.coalescer.ruby_system = ruby_system 20011768SCurtis.Dunham@arm.com self.coalescer.support_inst_reqs = False 20111768SCurtis.Dunham@arm.com self.coalescer.is_cpu_sequencer = False 20211768SCurtis.Dunham@arm.com 20311768SCurtis.Dunham@arm.com self.sequencer = RubySequencer() 20410037SARM gem5 Developers self.sequencer.version = self.seqCount() 20510037SARM gem5 Developers self.sequencer.icache = self.L1cache 20610037SARM gem5 Developers self.sequencer.dcache = self.L1cache 2079384SAndreas.Sandberg@arm.com self.sequencer.ruby_system = ruby_system 20810461SAndreas.Sandberg@ARM.com self.sequencer.is_cpu_sequencer = True 20910461SAndreas.Sandberg@ARM.com 21011165SRekai.GonzalezAlberquilla@arm.com self.use_seq_not_coal = True 21110461SAndreas.Sandberg@ARM.com 21210461SAndreas.Sandberg@ARM.com self.ruby_system = ruby_system 2139384SAndreas.Sandberg@arm.com 21411770SCurtis.Dunham@arm.com if options.recycle_latency: 21510037SARM gem5 Developers self.recycle_latency = options.recycle_latency 21610461SAndreas.Sandberg@ARM.com 21710461SAndreas.Sandberg@ARM.comclass SQCCache(RubyCache): 21810461SAndreas.Sandberg@ARM.com size = "32kB" 21910461SAndreas.Sandberg@ARM.com assoc = 8 22010461SAndreas.Sandberg@ARM.com dataArrayBanks = 16 22110461SAndreas.Sandberg@ARM.com tagArrayBanks = 4 22210609Sandreas.sandberg@arm.com dataAccessLatency = 4 22310609Sandreas.sandberg@arm.com tagAccessLatency = 1 22410609Sandreas.sandberg@arm.com def create(self, options): 22510037SARM gem5 Developers self.replacement_policy = PseudoLRUReplacementPolicy() 22610037SARM gem5 Developers 22710037SARM gem5 Developersclass SQCCntrl(SQC_Controller, CntrlBase): 22810037SARM gem5 Developers 22910037SARM gem5 Developers def create(self, options, ruby_system, system): 23010037SARM gem5 Developers self.version = self.versionCount() 23110037SARM gem5 Developers 23210037SARM gem5 Developers self.L1cache = SQCCache() 23310037SARM gem5 Developers self.L1cache.create(options) 23410037SARM gem5 Developers self.L1cache.resourceStalls = options.no_resource_stalls 23510037SARM gem5 Developers 23610037SARM gem5 Developers self.sequencer = RubySequencer() 23710037SARM gem5 Developers 23810037SARM gem5 Developers self.sequencer.version = self.seqCount() 23910037SARM gem5 Developers self.sequencer.icache = self.L1cache 24010037SARM gem5 Developers self.sequencer.dcache = self.L1cache 24111768SCurtis.Dunham@arm.com self.sequencer.ruby_system = ruby_system 24211768SCurtis.Dunham@arm.com self.sequencer.support_data_reqs = False 24310037SARM gem5 Developers self.sequencer.is_cpu_sequencer = False 24410037SARM gem5 Developers 24510037SARM gem5 Developers self.ruby_system = ruby_system 24610037SARM gem5 Developers 2479384SAndreas.Sandberg@arm.com if options.recycle_latency: 2489384SAndreas.Sandberg@arm.com self.recycle_latency = options.recycle_latency 2499384SAndreas.Sandberg@arm.com 2509384SAndreas.Sandberg@arm.com def createCP(self, options, ruby_system, system): 2519384SAndreas.Sandberg@arm.com self.version = self.versionCount() 2529384SAndreas.Sandberg@arm.com 2539384SAndreas.Sandberg@arm.com self.L1cache = SQCCache() 2549384SAndreas.Sandberg@arm.com self.L1cache.create(options) 2559384SAndreas.Sandberg@arm.com self.L1cache.resourceStalls = options.no_resource_stalls 2567427Sgblack@eecs.umich.edu 2577427Sgblack@eecs.umich.edu self.sequencer = RubySequencer() 2587427Sgblack@eecs.umich.edu 2599385SAndreas.Sandberg@arm.com self.sequencer.version = self.seqCount() 2609385SAndreas.Sandberg@arm.com self.sequencer.icache = self.L1cache 2617427Sgblack@eecs.umich.edu self.sequencer.dcache = self.L1cache 2627427Sgblack@eecs.umich.edu self.sequencer.ruby_system = ruby_system 26310037SARM gem5 Developers self.sequencer.support_data_reqs = False 26410037SARM gem5 Developers 26510037SARM gem5 Developers self.ruby_system = ruby_system 26610037SARM gem5 Developers 26710037SARM gem5 Developers if options.recycle_latency: 26810037SARM gem5 Developers self.recycle_latency = options.recycle_latency 26910037SARM gem5 Developers 27010037SARM gem5 Developers 27110037SARM gem5 Developersclass TCC(RubyCache): 27210037SARM gem5 Developers assoc = 16 27310037SARM gem5 Developers dataAccessLatency = 8 27410037SARM gem5 Developers tagAccessLatency = 2 27510037SARM gem5 Developers resourceStalls = True 27610037SARM gem5 Developers def create(self, options): 2777427Sgblack@eecs.umich.edu self.size = MemorySize(options.tcc_size) 2787427Sgblack@eecs.umich.edu self.size = self.size / options.num_tccs 2797427Sgblack@eecs.umich.edu self.dataArrayBanks = 256 / options.num_tccs #number of data banks 2807427Sgblack@eecs.umich.edu self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 2817427Sgblack@eecs.umich.edu if ((self.size.value / long(self.assoc)) < 128): 2827427Sgblack@eecs.umich.edu self.size.value = long(128 * self.assoc) 28310037SARM gem5 Developers self.start_index_bit = math.log(options.cacheline_size, 2) + \ 28410037SARM gem5 Developers math.log(options.num_tccs, 2) 28510037SARM gem5 Developers self.replacement_policy = PseudoLRUReplacementPolicy() 28610037SARM gem5 Developers 2877427Sgblack@eecs.umich.educlass TCCCntrl(TCC_Controller, CntrlBase): 2887427Sgblack@eecs.umich.edu def create(self, options, ruby_system, system): 2897427Sgblack@eecs.umich.edu self.version = self.versionCount() 29010037SARM gem5 Developers self.L2cache = TCC() 29110204SAli.Saidi@ARM.com self.L2cache.create(options) 29210204SAli.Saidi@ARM.com self.l2_response_latency = options.TCC_latency 29310037SARM gem5 Developers 2947427Sgblack@eecs.umich.edu self.number_of_TBEs = 2048 29510037SARM gem5 Developers 2967427Sgblack@eecs.umich.edu self.ruby_system = ruby_system 29710037SARM gem5 Developers 2987427Sgblack@eecs.umich.edu if options.recycle_latency: 2997427Sgblack@eecs.umich.edu self.recycle_latency = options.recycle_latency 30010037SARM gem5 Developers 3017427Sgblack@eecs.umich.edu def connectWireBuffers(self, req_to_tccdir, resp_to_tccdir, 3027427Sgblack@eecs.umich.edu tcc_unblock_to_tccdir, req_to_tcc, 3037427Sgblack@eecs.umich.edu probe_to_tcc, resp_to_tcc): 3047427Sgblack@eecs.umich.edu self.w_reqToTCCDir = req_to_tccdir 3057427Sgblack@eecs.umich.edu self.w_respToTCCDir = resp_to_tccdir 3067427Sgblack@eecs.umich.edu self.w_TCCUnblockToTCCDir = tcc_unblock_to_tccdir 3077427Sgblack@eecs.umich.edu self.w_reqToTCC = req_to_tcc 3087427Sgblack@eecs.umich.edu self.w_probeToTCC = probe_to_tcc 3097427Sgblack@eecs.umich.edu self.w_respToTCC = resp_to_tcc 3107427Sgblack@eecs.umich.edu 3117427Sgblack@eecs.umich.educlass TCCDirCntrl(TCCdir_Controller, CntrlBase): 3127427Sgblack@eecs.umich.edu def create(self, options, ruby_system, system): 3137427Sgblack@eecs.umich.edu self.version = self.versionCount() 3147427Sgblack@eecs.umich.edu 3157427Sgblack@eecs.umich.edu self.directory = TccDirCache() 3167427Sgblack@eecs.umich.edu self.directory.create(options) 3177427Sgblack@eecs.umich.edu 3187427Sgblack@eecs.umich.edu self.number_of_TBEs = 1024 3197427Sgblack@eecs.umich.edu 3207427Sgblack@eecs.umich.edu self.ruby_system = ruby_system 3217427Sgblack@eecs.umich.edu 3227427Sgblack@eecs.umich.edu if options.recycle_latency: 3237427Sgblack@eecs.umich.edu self.recycle_latency = options.recycle_latency 3247436Sdam.sunwoo@arm.com 3257436Sdam.sunwoo@arm.com def connectWireBuffers(self, req_to_tccdir, resp_to_tccdir, 32610037SARM gem5 Developers tcc_unblock_to_tccdir, req_to_tcc, 32710037SARM gem5 Developers probe_to_tcc, resp_to_tcc): 3287436Sdam.sunwoo@arm.com self.w_reqToTCCDir = req_to_tccdir 3297436Sdam.sunwoo@arm.com self.w_respToTCCDir = resp_to_tccdir 3307436Sdam.sunwoo@arm.com self.w_TCCUnblockToTCCDir = tcc_unblock_to_tccdir 3317436Sdam.sunwoo@arm.com self.w_reqToTCC = req_to_tcc 3327436Sdam.sunwoo@arm.com self.w_probeToTCC = probe_to_tcc 3337436Sdam.sunwoo@arm.com self.w_respToTCC = resp_to_tcc 3347436Sdam.sunwoo@arm.com 3357436Sdam.sunwoo@arm.comclass L3Cache(RubyCache): 3367436Sdam.sunwoo@arm.com assoc = 8 3377436Sdam.sunwoo@arm.com dataArrayBanks = 256 3387436Sdam.sunwoo@arm.com tagArrayBanks = 256 3397436Sdam.sunwoo@arm.com 34010037SARM gem5 Developers def create(self, options, ruby_system, system): 3417436Sdam.sunwoo@arm.com self.size = MemorySize(options.l3_size) 3427436Sdam.sunwoo@arm.com self.size.value /= options.num_dirs 3437436Sdam.sunwoo@arm.com self.dataArrayBanks /= options.num_dirs 3447436Sdam.sunwoo@arm.com self.tagArrayBanks /= options.num_dirs 3457436Sdam.sunwoo@arm.com self.dataArrayBanks /= options.num_dirs 3467436Sdam.sunwoo@arm.com self.tagArrayBanks /= options.num_dirs 3477436Sdam.sunwoo@arm.com self.dataAccessLatency = options.l3_data_latency 3487436Sdam.sunwoo@arm.com self.tagAccessLatency = options.l3_tag_latency 3497436Sdam.sunwoo@arm.com self.resourceStalls = options.no_resource_stalls 3507436Sdam.sunwoo@arm.com self.replacement_policy = PseudoLRUReplacementPolicy() 3517436Sdam.sunwoo@arm.com 3527436Sdam.sunwoo@arm.comclass L3Cntrl(L3Cache_Controller, CntrlBase): 3537436Sdam.sunwoo@arm.com def create(self, options, ruby_system, system): 3547436Sdam.sunwoo@arm.com self.version = self.versionCount() 3557436Sdam.sunwoo@arm.com self.L3cache = L3Cache() 3567436Sdam.sunwoo@arm.com self.L3cache.create(options, ruby_system, system) 3577644Sali.saidi@arm.com 3588147SAli.Saidi@ARM.com self.l3_response_latency = max(self.L3cache.dataAccessLatency, 3599385SAndreas.Sandberg@arm.com self.L3cache.tagAccessLatency) 3609385SAndreas.Sandberg@arm.com self.ruby_system = ruby_system 3619385SAndreas.Sandberg@arm.com 3629385SAndreas.Sandberg@arm.com if options.recycle_latency: 3639385SAndreas.Sandberg@arm.com self.recycle_latency = options.recycle_latency 3649385SAndreas.Sandberg@arm.com 3659385SAndreas.Sandberg@arm.com def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 3669385SAndreas.Sandberg@arm.com req_to_l3, probe_to_l3, resp_to_l3): 3679385SAndreas.Sandberg@arm.com self.reqToDir = req_to_dir 3689385SAndreas.Sandberg@arm.com self.respToDir = resp_to_dir 3699385SAndreas.Sandberg@arm.com self.l3UnblockToDir = l3_unblock_to_dir 3709385SAndreas.Sandberg@arm.com self.reqToL3 = req_to_l3 3719385SAndreas.Sandberg@arm.com self.probeToL3 = probe_to_l3 3729385SAndreas.Sandberg@arm.com self.respToL3 = resp_to_l3 3739385SAndreas.Sandberg@arm.com 3749385SAndreas.Sandberg@arm.comclass DirMem(RubyDirectoryMemory, CntrlBase): 3759385SAndreas.Sandberg@arm.com def create(self, options, ruby_system, system): 3769385SAndreas.Sandberg@arm.com self.version = self.versionCount() 37710037SARM gem5 Developers 37810037SARM gem5 Developers phys_mem_size = AddrRange(options.mem_size).size() 37910037SARM gem5 Developers mem_module_size = phys_mem_size / options.num_dirs 38010037SARM gem5 Developers dir_size = MemorySize('0B') 38110037SARM gem5 Developers dir_size.value = mem_module_size 38210037SARM gem5 Developers self.size = dir_size 38310037SARM gem5 Developers 38410037SARM gem5 Developersclass DirCntrl(Directory_Controller, CntrlBase): 38510037SARM gem5 Developers def create(self, options, ruby_system, system): 38610037SARM gem5 Developers self.version = self.versionCount() 38710037SARM gem5 Developers 38810037SARM gem5 Developers self.response_latency = 30 38910037SARM gem5 Developers 39010037SARM gem5 Developers self.directory = DirMem() 39110037SARM gem5 Developers self.directory.create(options, ruby_system, system) 39210037SARM gem5 Developers 3938147SAli.Saidi@ARM.com self.L3CacheMemory = L3Cache() 3947427Sgblack@eecs.umich.edu self.L3CacheMemory.create(options, ruby_system, system) 3957427Sgblack@eecs.umich.edu 3967427Sgblack@eecs.umich.edu self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 39710037SARM gem5 Developers self.L3CacheMemory.tagAccessLatency) 39810037SARM gem5 Developers 39910037SARM gem5 Developers self.number_of_TBEs = options.num_tbes 40010037SARM gem5 Developers 40110037SARM gem5 Developers self.ruby_system = ruby_system 40210037SARM gem5 Developers 40310037SARM gem5 Developers if options.recycle_latency: 40410037SARM gem5 Developers self.recycle_latency = options.recycle_latency 40510037SARM gem5 Developers 40610037SARM gem5 Developers def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 40710037SARM gem5 Developers req_to_l3, probe_to_l3, resp_to_l3): 40810037SARM gem5 Developers self.reqToDir = req_to_dir 40910037SARM gem5 Developers self.respToDir = resp_to_dir 41010037SARM gem5 Developers self.l3UnblockToDir = l3_unblock_to_dir 41110037SARM gem5 Developers self.reqToL3 = req_to_l3 41210037SARM gem5 Developers self.probeToL3 = probe_to_l3 41310037SARM gem5 Developers self.respToL3 = resp_to_l3 41410037SARM gem5 Developers 41510037SARM gem5 Developers 41610037SARM gem5 Developers 41710037SARM gem5 Developersdef define_options(parser): 41810037SARM gem5 Developers parser.add_option("--num-subcaches", type="int", default=4) 41910037SARM gem5 Developers parser.add_option("--l3-data-latency", type="int", default=20) 42010037SARM gem5 Developers parser.add_option("--l3-tag-latency", type="int", default=15) 42110037SARM gem5 Developers parser.add_option("--cpu-to-dir-latency", type="int", default=15) 42210037SARM gem5 Developers parser.add_option("--gpu-to-dir-latency", type="int", default=160) 42310037SARM gem5 Developers parser.add_option("--no-resource-stalls", action="store_false", 42410037SARM gem5 Developers default=True) 42510037SARM gem5 Developers parser.add_option("--num-tbes", type="int", default=256) 42610037SARM gem5 Developers parser.add_option("--l2-latency", type="int", default=50) # load to use 42710037SARM gem5 Developers parser.add_option("--num-tccs", type="int", default=1, 42810037SARM gem5 Developers help="number of TCC directories and banks in the GPU") 42910037SARM gem5 Developers parser.add_option("--TCP_latency", type="int", default=4, 43010037SARM gem5 Developers help="TCP latency") 43110037SARM gem5 Developers parser.add_option("--TCC_latency", type="int", default=16, 43210037SARM gem5 Developers help="TCC latency") 43311770SCurtis.Dunham@arm.com parser.add_option("--tcc-size", type='string', default='256kB', 43410037SARM gem5 Developers help="agregate tcc size") 43511574SCurtis.Dunham@arm.com parser.add_option("--tcp-size", type='string', default='16kB', 43611770SCurtis.Dunham@arm.com help="tcp size") 43711770SCurtis.Dunham@arm.com parser.add_option("--tcc-dir-factor", type='int', default=4, 43810037SARM gem5 Developers help="TCCdir size = factor *(TCPs + TCC)") 43911770SCurtis.Dunham@arm.com 44011770SCurtis.Dunham@arm.comdef create_system(options, full_system, system, dma_devices, ruby_system): 44110037SARM gem5 Developers if buildEnv['PROTOCOL'] != 'GPU_RfO': 44210037SARM gem5 Developers panic("This script requires the GPU_RfO protocol to be built.") 44310037SARM gem5 Developers 44410037SARM gem5 Developers cpu_sequencers = [] 44510037SARM gem5 Developers 44610037SARM gem5 Developers # 44710037SARM gem5 Developers # The ruby network creation expects the list of nodes in the system to be 44810461SAndreas.Sandberg@ARM.com # consistent with the NetDest list. Therefore the l1 controller nodes 44910461SAndreas.Sandberg@ARM.com # must be listed before the directory nodes and directory nodes before 45010461SAndreas.Sandberg@ARM.com # dma nodes, etc. 45110461SAndreas.Sandberg@ARM.com # 45210037SARM gem5 Developers cp_cntrl_nodes = [] 45310037SARM gem5 Developers tcp_cntrl_nodes = [] 45410037SARM gem5 Developers sqc_cntrl_nodes = [] 45510037SARM gem5 Developers tcc_cntrl_nodes = [] 45610037SARM gem5 Developers tccdir_cntrl_nodes = [] 45710037SARM gem5 Developers dir_cntrl_nodes = [] 45810037SARM gem5 Developers l3_cntrl_nodes = [] 45910037SARM gem5 Developers 46010461SAndreas.Sandberg@ARM.com # 46110461SAndreas.Sandberg@ARM.com # Must create the individual controllers before the network to ensure the 46210461SAndreas.Sandberg@ARM.com # controller constructors are called before the network constructor 46310461SAndreas.Sandberg@ARM.com # 46410461SAndreas.Sandberg@ARM.com 46510037SARM gem5 Developers TCC_bits = int(math.log(options.num_tccs, 2)) 46610037SARM gem5 Developers 46710037SARM gem5 Developers # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 46810037SARM gem5 Developers # Clusters 46910037SARM gem5 Developers mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 47011574SCurtis.Dunham@arm.com for i in xrange(options.num_dirs): 47110037SARM gem5 Developers 47210037SARM gem5 Developers dir_cntrl = DirCntrl(TCC_select_num_bits = TCC_bits) 47310037SARM gem5 Developers dir_cntrl.create(options, ruby_system, system) 47411574SCurtis.Dunham@arm.com dir_cntrl.number_of_TBEs = 2560 * options.num_compute_units 47510037SARM gem5 Developers #Enough TBEs for all TCP TBEs 47610037SARM gem5 Developers 47710037SARM gem5 Developers # Connect the Directory controller to the ruby network 47810037SARM gem5 Developers dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 47910037SARM gem5 Developers dir_cntrl.requestFromCores.slave = ruby_system.network.master 48010037SARM gem5 Developers 48110037SARM gem5 Developers dir_cntrl.responseFromCores = MessageBuffer() 48210037SARM gem5 Developers dir_cntrl.responseFromCores.slave = ruby_system.network.master 48310037SARM gem5 Developers 48410037SARM gem5 Developers dir_cntrl.unblockFromCores = MessageBuffer() 4857405SAli.Saidi@ARM.com dir_cntrl.unblockFromCores.slave = ruby_system.network.master 48610035Sandreas.hansson@arm.com 4877405SAli.Saidi@ARM.com dir_cntrl.probeToCore = MessageBuffer() 4887405SAli.Saidi@ARM.com dir_cntrl.probeToCore.master = ruby_system.network.slave 4897614Sminkyu.jeong@arm.com 49010037SARM gem5 Developers dir_cntrl.responseToCore = MessageBuffer() 49110037SARM gem5 Developers dir_cntrl.responseToCore.master = ruby_system.network.slave 49210037SARM gem5 Developers 4937614Sminkyu.jeong@arm.com dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 49411770SCurtis.Dunham@arm.com dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 49510037SARM gem5 Developers dir_cntrl.responseFromMemory = MessageBuffer() 49610037SARM gem5 Developers 49710037SARM gem5 Developers exec("system.dir_cntrl%d = dir_cntrl" % i) 49810037SARM gem5 Developers dir_cntrl_nodes.append(dir_cntrl) 49910037SARM gem5 Developers 50010037SARM gem5 Developers mainCluster.add(dir_cntrl) 50110037SARM gem5 Developers 50210037SARM gem5 Developers # For an odd number of CPUs, still create the right number of controllers 50310037SARM gem5 Developers cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 50410037SARM gem5 Developers for i in xrange((options.num_cpus + 1) / 2): 5057614Sminkyu.jeong@arm.com 5067405SAli.Saidi@ARM.com cp_cntrl = CPCntrl() 5077405SAli.Saidi@ARM.com cp_cntrl.create(options, ruby_system, system) 5087405SAli.Saidi@ARM.com 5097405SAli.Saidi@ARM.com exec("system.cp_cntrl%d = cp_cntrl" % i) 5107405SAli.Saidi@ARM.com # 5117405SAli.Saidi@ARM.com # Add controllers and sequencers to the appropriate lists 51210037SARM gem5 Developers # 51310037SARM gem5 Developers cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 51410037SARM gem5 Developers 5159050Schander.sudanthi@arm.com # Connect the CP controllers and the network 5167405SAli.Saidi@ARM.com cp_cntrl.requestFromCore = MessageBuffer() 51710037SARM gem5 Developers cp_cntrl.requestFromCore.master = ruby_system.network.slave 51810037SARM gem5 Developers 5197720Sgblack@eecs.umich.edu cp_cntrl.responseFromCore = MessageBuffer() 5207720Sgblack@eecs.umich.edu cp_cntrl.responseFromCore.master = ruby_system.network.slave 5217405SAli.Saidi@ARM.com 5227405SAli.Saidi@ARM.com cp_cntrl.unblockFromCore = MessageBuffer() 5237757SAli.Saidi@ARM.com cp_cntrl.unblockFromCore.master = ruby_system.network.slave 52410037SARM gem5 Developers 52510037SARM gem5 Developers cp_cntrl.probeToCore = MessageBuffer() 52610037SARM gem5 Developers cp_cntrl.probeToCore.slave = ruby_system.network.master 52710037SARM gem5 Developers 52810037SARM gem5 Developers cp_cntrl.responseToCore = MessageBuffer() 52910037SARM gem5 Developers cp_cntrl.responseToCore.slave = ruby_system.network.master 53010037SARM gem5 Developers 53110037SARM gem5 Developers cp_cntrl.mandatoryQueue = MessageBuffer() 53210037SARM gem5 Developers cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 53310037SARM gem5 Developers 53410037SARM gem5 Developers cpuCluster.add(cp_cntrl) 53510037SARM gem5 Developers 53610037SARM gem5 Developers gpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s 53710037SARM gem5 Developers 53810037SARM gem5 Developers for i in xrange(options.num_compute_units): 53910037SARM gem5 Developers 54010037SARM gem5 Developers tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 54110037SARM gem5 Developers number_of_TBEs = 2560) # max outstanding requests 54210037SARM gem5 Developers tcp_cntrl.create(options, ruby_system, system) 54310037SARM gem5 Developers 54410037SARM gem5 Developers exec("system.tcp_cntrl%d = tcp_cntrl" % i) 54510037SARM gem5 Developers # 54610037SARM gem5 Developers # Add controllers and sequencers to the appropriate lists 54710037SARM gem5 Developers # 54810037SARM gem5 Developers cpu_sequencers.append(tcp_cntrl.coalescer) 54910037SARM gem5 Developers tcp_cntrl_nodes.append(tcp_cntrl) 55010037SARM gem5 Developers 55110037SARM gem5 Developers # Connect the TCP controller to the ruby network 55210037SARM gem5 Developers tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 55310037SARM gem5 Developers tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 55410037SARM gem5 Developers 55510037SARM gem5 Developers tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 55610037SARM gem5 Developers tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 55710037SARM gem5 Developers 55810037SARM gem5 Developers tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True) 55910037SARM gem5 Developers tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 56010037SARM gem5 Developers 56110037SARM gem5 Developers tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 56210037SARM gem5 Developers tcp_cntrl.probeToTCP.slave = ruby_system.network.master 56310037SARM gem5 Developers 56410037SARM gem5 Developers tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 56510037SARM gem5 Developers tcp_cntrl.responseToTCP.slave = ruby_system.network.master 56610037SARM gem5 Developers 56710037SARM gem5 Developers tcp_cntrl.mandatoryQueue = MessageBuffer() 56810037SARM gem5 Developers 56910037SARM gem5 Developers gpuCluster.add(tcp_cntrl) 5708284SAli.Saidi@ARM.com 57110037SARM gem5 Developers for i in xrange(options.num_sqc): 57210037SARM gem5 Developers 57310037SARM gem5 Developers sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 57410037SARM gem5 Developers sqc_cntrl.create(options, ruby_system, system) 5759050Schander.sudanthi@arm.com 57610037SARM gem5 Developers exec("system.sqc_cntrl%d = sqc_cntrl" % i) 57710037SARM gem5 Developers # 57810037SARM gem5 Developers # Add controllers and sequencers to the appropriate lists 57910037SARM gem5 Developers # 58010037SARM gem5 Developers cpu_sequencers.append(sqc_cntrl.sequencer) 58110037SARM gem5 Developers 58210037SARM gem5 Developers # Connect the SQC controller to the ruby network 58310037SARM gem5 Developers sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 58410037SARM gem5 Developers sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 58510037SARM gem5 Developers 58610037SARM gem5 Developers sqc_cntrl.responseFromSQC = MessageBuffer(ordered = True) 58710037SARM gem5 Developers sqc_cntrl.responseFromSQC.master = ruby_system.network.slave 58810037SARM gem5 Developers 58910037SARM gem5 Developers sqc_cntrl.unblockFromCore = MessageBuffer(ordered = True) 59010037SARM gem5 Developers sqc_cntrl.unblockFromCore.master = ruby_system.network.slave 59110037SARM gem5 Developers 59210037SARM gem5 Developers sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 59310037SARM gem5 Developers sqc_cntrl.probeToSQC.slave = ruby_system.network.master 5949050Schander.sudanthi@arm.com 5958284SAli.Saidi@ARM.com sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 59610037SARM gem5 Developers sqc_cntrl.responseToSQC.slave = ruby_system.network.master 59710037SARM gem5 Developers 59810037SARM gem5 Developers sqc_cntrl.mandatoryQueue = MessageBuffer() 59910037SARM gem5 Developers 60010037SARM gem5 Developers # SQC also in GPU cluster 60110037SARM gem5 Developers gpuCluster.add(sqc_cntrl) 60210037SARM gem5 Developers 6037405SAli.Saidi@ARM.com for i in xrange(options.num_cp): 6047731SAli.Saidi@ARM.com 6058468Swade.walker@arm.com tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 6068468Swade.walker@arm.com number_of_TBEs = 2560) # max outstanding requests 6078468Swade.walker@arm.com tcp_cntrl.createCP(options, ruby_system, system) 6087405SAli.Saidi@ARM.com 6097731SAli.Saidi@ARM.com exec("system.tcp_cntrl%d = tcp_cntrl" % (options.num_compute_units + i)) 6107405SAli.Saidi@ARM.com # 6117405SAli.Saidi@ARM.com # Add controllers and sequencers to the appropriate lists 6127583SAli.Saidi@arm.com # 6139130Satgutier@umich.edu cpu_sequencers.append(tcp_cntrl.sequencer) 6149130Satgutier@umich.edu tcp_cntrl_nodes.append(tcp_cntrl) 6159130Satgutier@umich.edu 6169130Satgutier@umich.edu # Connect the TCP controller to the ruby network 6179814Sandreas.hansson@arm.com tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 6189130Satgutier@umich.edu tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 6199130Satgutier@umich.edu 6209130Satgutier@umich.edu tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 6219130Satgutier@umich.edu tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 6229130Satgutier@umich.edu 6239130Satgutier@umich.edu tcp_cntrl.unblockFromCore = MessageBuffer(ordered = True) 6249130Satgutier@umich.edu tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 6259130Satgutier@umich.edu 6269130Satgutier@umich.edu tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 6279130Satgutier@umich.edu tcp_cntrl.probeToTCP.slave = ruby_system.network.master 6289130Satgutier@umich.edu 6299130Satgutier@umich.edu tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 6309130Satgutier@umich.edu tcp_cntrl.responseToTCP.slave = ruby_system.network.master 6319130Satgutier@umich.edu 6329130Satgutier@umich.edu tcp_cntrl.mandatoryQueue = MessageBuffer() 6339130Satgutier@umich.edu 6349130Satgutier@umich.edu gpuCluster.add(tcp_cntrl) 6359130Satgutier@umich.edu 6369130Satgutier@umich.edu sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 6379130Satgutier@umich.edu sqc_cntrl.createCP(options, ruby_system, system) 6389130Satgutier@umich.edu 6399130Satgutier@umich.edu exec("system.sqc_cntrl%d = sqc_cntrl" % (options.num_compute_units + i)) 6407583SAli.Saidi@arm.com # 6417583SAli.Saidi@arm.com # Add controllers and sequencers to the appropriate lists 6427583SAli.Saidi@arm.com # 64310461SAndreas.Sandberg@ARM.com cpu_sequencers.append(sqc_cntrl.sequencer) 64410461SAndreas.Sandberg@ARM.com 64510461SAndreas.Sandberg@ARM.com # Connect the SQC controller to the ruby network 64610461SAndreas.Sandberg@ARM.com sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 64710461SAndreas.Sandberg@ARM.com sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 64810461SAndreas.Sandberg@ARM.com 64910461SAndreas.Sandberg@ARM.com sqc_cntrl.responseFromSQC = MessageBuffer(ordered = True) 6508302SAli.Saidi@ARM.com sqc_cntrl.responseFromSQC.master = ruby_system.network.slave 6518302SAli.Saidi@ARM.com 6527783SGiacomo.Gabrielli@arm.com sqc_cntrl.unblockFromCore = MessageBuffer(ordered = True) 6537783SGiacomo.Gabrielli@arm.com sqc_cntrl.unblockFromCore.master = ruby_system.network.slave 6547783SGiacomo.Gabrielli@arm.com 6557783SGiacomo.Gabrielli@arm.com sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 65610037SARM gem5 Developers sqc_cntrl.probeToSQC.slave = ruby_system.network.master 65710037SARM gem5 Developers 65810037SARM gem5 Developers sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 65910037SARM gem5 Developers sqc_cntrl.responseToSQC.slave = ruby_system.network.master 66010037SARM gem5 Developers 66110037SARM gem5 Developers sqc_cntrl.mandatoryQueue = MessageBuffer() 66210037SARM gem5 Developers 66310037SARM gem5 Developers # SQC also in GPU cluster 66410037SARM gem5 Developers gpuCluster.add(sqc_cntrl) 66510037SARM gem5 Developers 66610037SARM gem5 Developers for i in xrange(options.num_tccs): 66710037SARM gem5 Developers 66810037SARM gem5 Developers tcc_cntrl = TCCCntrl(TCC_select_num_bits = TCC_bits, 66910037SARM gem5 Developers number_of_TBEs = options.num_compute_units * 2560) 67010037SARM gem5 Developers #Enough TBEs for all TCP TBEs 67110037SARM gem5 Developers tcc_cntrl.create(options, ruby_system, system) 67210037SARM gem5 Developers tcc_cntrl_nodes.append(tcc_cntrl) 67310037SARM gem5 Developers 67410037SARM gem5 Developers tccdir_cntrl = TCCDirCntrl(TCC_select_num_bits = TCC_bits, 67510037SARM gem5 Developers number_of_TBEs = options.num_compute_units * 2560) 67610037SARM gem5 Developers #Enough TBEs for all TCP TBEs 67710037SARM gem5 Developers tccdir_cntrl.create(options, ruby_system, system) 67810037SARM gem5 Developers tccdir_cntrl_nodes.append(tccdir_cntrl) 67910037SARM gem5 Developers 68010037SARM gem5 Developers exec("system.tcc_cntrl%d = tcc_cntrl" % i) 68110037SARM gem5 Developers exec("system.tccdir_cntrl%d = tccdir_cntrl" % i) 68210037SARM gem5 Developers 68310037SARM gem5 Developers # connect all of the wire buffers between L3 and dirs up 68410037SARM gem5 Developers req_to_tccdir = RubyWireBuffer() 68510037SARM gem5 Developers resp_to_tccdir = RubyWireBuffer() 68610037SARM gem5 Developers tcc_unblock_to_tccdir = RubyWireBuffer() 68710037SARM gem5 Developers req_to_tcc = RubyWireBuffer() 68810037SARM gem5 Developers probe_to_tcc = RubyWireBuffer() 68910037SARM gem5 Developers resp_to_tcc = RubyWireBuffer() 69010037SARM gem5 Developers 69110037SARM gem5 Developers tcc_cntrl.connectWireBuffers(req_to_tccdir, resp_to_tccdir, 69210037SARM gem5 Developers tcc_unblock_to_tccdir, req_to_tcc, 69310037SARM gem5 Developers probe_to_tcc, resp_to_tcc) 69410338SCurtis.Dunham@arm.com tccdir_cntrl.connectWireBuffers(req_to_tccdir, resp_to_tccdir, 69510338SCurtis.Dunham@arm.com tcc_unblock_to_tccdir, req_to_tcc, 69610338SCurtis.Dunham@arm.com probe_to_tcc, resp_to_tcc) 69710037SARM gem5 Developers 69810037SARM gem5 Developers # Connect the TCC controller to the ruby network 69910037SARM gem5 Developers tcc_cntrl.responseFromTCC = MessageBuffer(ordered = True) 70010037SARM gem5 Developers tcc_cntrl.responseFromTCC.master = ruby_system.network.slave 70110037SARM gem5 Developers 70210037SARM gem5 Developers tcc_cntrl.responseToTCC = MessageBuffer(ordered = True) 70310037SARM gem5 Developers tcc_cntrl.responseToTCC.slave = ruby_system.network.master 70410037SARM gem5 Developers 70510037SARM gem5 Developers # Connect the TCC Dir controller to the ruby network 70610037SARM gem5 Developers tccdir_cntrl.requestFromTCP = MessageBuffer(ordered = True) 70710037SARM gem5 Developers tccdir_cntrl.requestFromTCP.slave = ruby_system.network.master 70810037SARM gem5 Developers 70910037SARM gem5 Developers tccdir_cntrl.responseFromTCP = MessageBuffer(ordered = True) 71010037SARM gem5 Developers tccdir_cntrl.responseFromTCP.slave = ruby_system.network.master 71110037SARM gem5 Developers 71210037SARM gem5 Developers tccdir_cntrl.unblockFromTCP = MessageBuffer(ordered = True) 71310037SARM gem5 Developers tccdir_cntrl.unblockFromTCP.slave = ruby_system.network.master 71410037SARM gem5 Developers 71510037SARM gem5 Developers tccdir_cntrl.probeToCore = MessageBuffer(ordered = True) 71610037SARM gem5 Developers tccdir_cntrl.probeToCore.master = ruby_system.network.slave 71710037SARM gem5 Developers 71810037SARM gem5 Developers tccdir_cntrl.responseToCore = MessageBuffer(ordered = True) 71910037SARM gem5 Developers tccdir_cntrl.responseToCore.master = ruby_system.network.slave 72010037SARM gem5 Developers 72110037SARM gem5 Developers tccdir_cntrl.probeFromNB = MessageBuffer() 72210037SARM gem5 Developers tccdir_cntrl.probeFromNB.slave = ruby_system.network.master 72310037SARM gem5 Developers 72410037SARM gem5 Developers tccdir_cntrl.responseFromNB = MessageBuffer() 7258549Sdaniel.johnson@arm.com tccdir_cntrl.responseFromNB.slave = ruby_system.network.master 7268868SMatt.Horsnell@arm.com 7278868SMatt.Horsnell@arm.com tccdir_cntrl.requestToNB = MessageBuffer() 7288868SMatt.Horsnell@arm.com tccdir_cntrl.requestToNB.master = ruby_system.network.slave 7298868SMatt.Horsnell@arm.com 7308868SMatt.Horsnell@arm.com tccdir_cntrl.responseToNB = MessageBuffer() 7318868SMatt.Horsnell@arm.com tccdir_cntrl.responseToNB.master = ruby_system.network.slave 7328868SMatt.Horsnell@arm.com 7338868SMatt.Horsnell@arm.com tccdir_cntrl.unblockToNB = MessageBuffer() 7348868SMatt.Horsnell@arm.com tccdir_cntrl.unblockToNB.master = ruby_system.network.slave 73510461SAndreas.Sandberg@ARM.com 7368868SMatt.Horsnell@arm.com tccdir_cntrl.triggerQueue = MessageBuffer(ordered = True) 73710461SAndreas.Sandberg@ARM.com 73810037SARM gem5 Developers # TCC cntrls added to the GPU cluster 7398868SMatt.Horsnell@arm.com gpuCluster.add(tcc_cntrl) 74010037SARM gem5 Developers gpuCluster.add(tccdir_cntrl) 74111150Smitch.hayenga@arm.com 74210037SARM gem5 Developers # Assuming no DMA devices 74310037SARM gem5 Developers assert(len(dma_devices) == 0) 74410037SARM gem5 Developers 74510037SARM gem5 Developers # Add cpu/gpu clusters to main cluster 74611150Smitch.hayenga@arm.com mainCluster.add(cpuCluster) 74710037SARM gem5 Developers mainCluster.add(gpuCluster) 74810037SARM gem5 Developers 74910037SARM gem5 Developers ruby_system.network.number_of_virtual_networks = 10 75010037SARM gem5 Developers 75110037SARM gem5 Developers return (cpu_sequencers, dir_cntrl_nodes, mainCluster) 75210037SARM gem5 Developers