AMD_Base_Constructor.py revision 13400:cf74d21e948f 
1# Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#
9# 1. Redistributions of source code must retain the above copyright notice,
10# this list of conditions and the following disclaimer.
11#
12# 2. Redistributions in binary form must reproduce the above copyright notice,
13# this list of conditions and the following disclaimer in the documentation
14# and/or other materials provided with the distribution.
15#
16# 3. Neither the name of the copyright holder nor the names of its
17# contributors may be used to endorse or promote products derived from this
18# software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Sooraj Puthoor,
33#          Lisa Hsu
34
35import math
36import m5
37from m5.objects import *
38from m5.defines import buildEnv
39from m5.util import addToPath, convert
40from CntrlBase import *
41
42addToPath('../')
43
44from topologies.Cluster import Cluster
45
46#
47# Note: the L1 Cache latency is only used by the sequencer on fast path hits
48#
49class L1Cache(RubyCache):
50    latency = 1
51    resourceStalls = False
52    def create(self, size, assoc, options):
53        self.size = MemorySize(size)
54        self.assoc = assoc
55        self.replacement_policy = PseudoLRUReplacementPolicy()
56
57#
58# Note: the L2 Cache latency is not currently used
59#
60class L2Cache(RubyCache):
61    latency = 10
62    resourceStalls = False
63    def create(self, size, assoc, options):
64        self.size = MemorySize(size)
65        self.assoc = assoc
66        self.replacement_policy = PseudoLRUReplacementPolicy()
67class CPCntrl(AMD_Base_Controller, CntrlBase):
68
69    def create(self, options, ruby_system, system):
70        self.version = self.versionCount()
71        self.cntrl_id = self.cntrlCount()
72
73        self.L1Icache = L1Cache()
74        self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
75        self.L1D0cache = L1Cache()
76        self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
77        self.L1D1cache = L1Cache()
78        self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
79        self.L2cache = L2Cache()
80        self.L2cache.create(options.l2_size, options.l2_assoc, options)
81
82        self.sequencer = RubySequencer()
83        self.sequencer.version = self.seqCount()
84        self.sequencer.icache = self.L1Icache
85        self.sequencer.dcache = self.L1D0cache
86        self.sequencer.ruby_system = ruby_system
87        self.sequencer.coreid = 0
88        self.sequencer.is_cpu_sequencer = True
89
90        self.sequencer1 = RubySequencer()
91        self.sequencer1.version = self.seqCount()
92        self.sequencer1.icache = self.L1Icache
93        self.sequencer1.dcache = self.L1D1cache
94        self.sequencer1.ruby_system = ruby_system
95        self.sequencer1.coreid = 1
96        self.sequencer1.is_cpu_sequencer = True
97
98        self.issue_latency = options.cpu_to_dir_latency
99        self.send_evictions = send_evicts(options)
100
101        self.ruby_system = ruby_system
102
103        if options.recycle_latency:
104            self.recycle_latency = options.recycle_latency
105
106def define_options(parser):
107    parser.add_option("--cpu-to-dir-latency", type="int", default=15)
108
109def construct(options, system, ruby_system):
110    if (buildEnv['PROTOCOL'] != 'GPU_VIPER' or
111        buildEnv['PROTOCOL'] != 'GPU_VIPER_Region' or
112        buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline'):
113        panic("This script requires VIPER based protocols \
114        to be built.")
115    cpu_sequencers = []
116    cpuCluster = None
117    cpuCluster = Cluster(name="CPU Cluster", extBW = 8, intBW=8) # 16 GB/s
118    for i in xrange((options.num_cpus + 1) / 2):
119
120        cp_cntrl = CPCntrl()
121        cp_cntrl.create(options, ruby_system, system)
122
123        # Connect the CP controllers to the ruby network
124        cp_cntrl.requestFromCore = ruby_system.network.slave
125        cp_cntrl.responseFromCore = ruby_system.network.slave
126        cp_cntrl.unblockFromCore = ruby_system.network.slave
127        cp_cntrl.probeToCore = ruby_system.network.master
128        cp_cntrl.responseToCore = ruby_system.network.master
129
130        exec("system.cp_cntrl%d = cp_cntrl" % i)
131        #
132        # Add controllers and sequencers to the appropriate lists
133        #
134        cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
135        cpuCluster.add(cp_cntrl)
136    return cpu_sequencers, cpuCluster
137