AMD_Base_Constructor.py revision 11670:6ce719503eae
1# 2# Copyright (c) 2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: 9# 10# 1. Redistributions of source code must retain the above copyright notice, 11# this list of conditions and the following disclaimer. 12# 13# 2. Redistributions in binary form must reproduce the above copyright notice, 14# this list of conditions and the following disclaimer in the documentation 15# and/or other materials provided with the distribution. 16# 17# 3. Neither the name of the copyright holder nor the names of its contributors 18# may be used to endorse or promote products derived from this software 19# without specific prior written permission. 20# 21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31# POSSIBILITY OF SUCH DAMAGE. 32# 33# Author: Sooraj Puthoor, Lisa Hsu 34# 35 36import math 37import m5 38from m5.objects import * 39from m5.defines import buildEnv 40from m5.util import convert 41from CntrlBase import * 42from topologies.Cluster import Cluster 43 44# 45# Note: the L1 Cache latency is only used by the sequencer on fast path hits 46# 47class L1Cache(RubyCache): 48 latency = 1 49 resourceStalls = False 50 def create(self, size, assoc, options): 51 self.size = MemorySize(size) 52 self.assoc = assoc 53 self.replacement_policy = PseudoLRUReplacementPolicy() 54 55# 56# Note: the L2 Cache latency is not currently used 57# 58class L2Cache(RubyCache): 59 latency = 10 60 resourceStalls = False 61 def create(self, size, assoc, options): 62 self.size = MemorySize(size) 63 self.assoc = assoc 64 self.replacement_policy = PseudoLRUReplacementPolicy() 65class CPCntrl(AMD_Base_Controller, CntrlBase): 66 67 def create(self, options, ruby_system, system): 68 self.version = self.versionCount() 69 self.cntrl_id = self.cntrlCount() 70 71 self.L1Icache = L1Cache() 72 self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 73 self.L1D0cache = L1Cache() 74 self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 75 self.L1D1cache = L1Cache() 76 self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 77 self.L2cache = L2Cache() 78 self.L2cache.create(options.l2_size, options.l2_assoc, options) 79 80 self.sequencer = RubySequencer() 81 self.sequencer.version = self.seqCount() 82 self.sequencer.icache = self.L1Icache 83 self.sequencer.dcache = self.L1D0cache 84 self.sequencer.ruby_system = ruby_system 85 self.sequencer.coreid = 0 86 self.sequencer.is_cpu_sequencer = True 87 88 self.sequencer1 = RubySequencer() 89 self.sequencer1.version = self.seqCount() 90 self.sequencer1.icache = self.L1Icache 91 self.sequencer1.dcache = self.L1D1cache 92 self.sequencer1.ruby_system = ruby_system 93 self.sequencer1.coreid = 1 94 self.sequencer1.is_cpu_sequencer = True 95 96 self.issue_latency = options.cpu_to_dir_latency 97 self.send_evictions = send_evicts(options) 98 99 self.ruby_system = ruby_system 100 101 if options.recycle_latency: 102 self.recycle_latency = options.recycle_latency 103 104def define_options(parser): 105 parser.add_option("--cpu-to-dir-latency", type="int", default=15) 106 107def construct(options, system, ruby_system): 108 if (buildEnv['PROTOCOL'] != 'GPU_VIPER' or 109 buildEnv['PROTOCOL'] != 'GPU_VIPER_Region' or 110 buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline'): 111 panic("This script requires VIPER based protocols \ 112 to be built.") 113 cpu_sequencers = [] 114 cpuCluster = None 115 cpuCluster = Cluster(name="CPU Cluster", extBW = 8, intBW=8) # 16 GB/s 116 for i in xrange((options.num_cpus + 1) / 2): 117 118 cp_cntrl = CPCntrl() 119 cp_cntrl.create(options, ruby_system, system) 120 121 # Connect the CP controllers to the ruby network 122 cp_cntrl.requestFromCore = ruby_system.network.slave 123 cp_cntrl.responseFromCore = ruby_system.network.slave 124 cp_cntrl.unblockFromCore = ruby_system.network.slave 125 cp_cntrl.probeToCore = ruby_system.network.master 126 cp_cntrl.responseToCore = ruby_system.network.master 127 128 exec("system.cp_cntrl%d = cp_cntrl" % i) 129 # 130 # Add controllers and sequencers to the appropriate lists 131 # 132 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 133 cpuCluster.add(cp_cntrl) 134 return cpu_sequencers, cpuCluster 135