test_caches.py revision 13774:a1be2a0c55f2
110461SAndreas.Sandberg@ARM.com# -*- coding: utf-8 -*- 212117Sjose.marinho@arm.com# Copyright (c) 2017 Jason Power 310461SAndreas.Sandberg@ARM.com# All rights reserved. 410461SAndreas.Sandberg@ARM.com# 510461SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 610461SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 710461SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 810461SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 910461SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 1010461SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 1110461SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 1210461SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 1310461SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 1410461SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 1510461SAndreas.Sandberg@ARM.com# 1610461SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710461SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810461SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910461SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010461SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110461SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210461SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310461SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410461SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510461SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610461SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710461SAndreas.Sandberg@ARM.com# 2810461SAndreas.Sandberg@ARM.com# Authors: Jason Power 2910461SAndreas.Sandberg@ARM.com 3010461SAndreas.Sandberg@ARM.com""" This file creates a set of Ruby caches, the Ruby network, and a simple 3110461SAndreas.Sandberg@ARM.compoint-to-point topology for the RubyRandomTester to use. 3210461SAndreas.Sandberg@ARM.comSee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 3310461SAndreas.Sandberg@ARM.com 3410461SAndreas.Sandberg@ARM.comIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 3510461SAndreas.Sandberg@ARM.com also needs to be updated. For now, email Jason <jason@lowepower.com> 3610461SAndreas.Sandberg@ARM.com 3710461SAndreas.Sandberg@ARM.com""" 3810461SAndreas.Sandberg@ARM.com 3910461SAndreas.Sandberg@ARM.comfrom __future__ import print_function 4010461SAndreas.Sandberg@ARM.comfrom __future__ import absolute_import 4110461SAndreas.Sandberg@ARM.com 4210461SAndreas.Sandberg@ARM.comfrom m5.defines import buildEnv 4310461SAndreas.Sandberg@ARM.comfrom m5.util import fatal 4410461SAndreas.Sandberg@ARM.com 4510461SAndreas.Sandberg@ARM.comfrom m5.objects import * 4610461SAndreas.Sandberg@ARM.com 4710461SAndreas.Sandberg@ARM.comfrom .msi_caches import L1Cache, DirController, MyNetwork 4810461SAndreas.Sandberg@ARM.com 4910461SAndreas.Sandberg@ARM.comclass TestCacheSystem(RubySystem): 5010461SAndreas.Sandberg@ARM.com 5110461SAndreas.Sandberg@ARM.com def __init__(self): 5210461SAndreas.Sandberg@ARM.com if buildEnv['PROTOCOL'] != 'MSI': 5310461SAndreas.Sandberg@ARM.com fatal("This system assumes MSI from learning gem5!") 5410461SAndreas.Sandberg@ARM.com 5510461SAndreas.Sandberg@ARM.com super(TestCacheSystem, self).__init__() 5610461SAndreas.Sandberg@ARM.com 5710461SAndreas.Sandberg@ARM.com def setup(self, system, tester, mem_ctrls): 5810461SAndreas.Sandberg@ARM.com """Set up the Ruby cache subsystem. Note: This can't be done in the 5910461SAndreas.Sandberg@ARM.com constructor because many of these items require a pointer to the 6010461SAndreas.Sandberg@ARM.com ruby system (self). This causes infinite recursion in initialize() 6110461SAndreas.Sandberg@ARM.com if we do this in the __init__. 6210461SAndreas.Sandberg@ARM.com Setting up for running the RubyRandomTester is a little different 6310461SAndreas.Sandberg@ARM.com than when we're using CPUs. 6410461SAndreas.Sandberg@ARM.com """ 6510461SAndreas.Sandberg@ARM.com num_testers = tester.num_cpus 6610461SAndreas.Sandberg@ARM.com 6710461SAndreas.Sandberg@ARM.com # Ruby's global network. 6810461SAndreas.Sandberg@ARM.com self.network = MyNetwork(self) 6910461SAndreas.Sandberg@ARM.com 7010461SAndreas.Sandberg@ARM.com # MSI uses 3 virtual networks 7110461SAndreas.Sandberg@ARM.com self.number_of_virtual_networks = 3 7210461SAndreas.Sandberg@ARM.com self.network.number_of_virtual_networks = 3 7310461SAndreas.Sandberg@ARM.com 7410461SAndreas.Sandberg@ARM.com self.controllers = \ 7510461SAndreas.Sandberg@ARM.com [L1Cache(system, self, self) for i in range(num_testers)] + \ 7610461SAndreas.Sandberg@ARM.com [DirController(self, system.mem_ranges, mem_ctrls)] 7710461SAndreas.Sandberg@ARM.com 7810461SAndreas.Sandberg@ARM.com self.sequencers = [RubySequencer(version = i, 7910461SAndreas.Sandberg@ARM.com # I/D cache is combined and grab from ctrl 8010461SAndreas.Sandberg@ARM.com icache = self.controllers[i].cacheMemory, 8110461SAndreas.Sandberg@ARM.com dcache = self.controllers[i].cacheMemory, 8210461SAndreas.Sandberg@ARM.com clk_domain = self.clk_domain, 8310461SAndreas.Sandberg@ARM.com ) for i in range(num_testers)] 8410461SAndreas.Sandberg@ARM.com 8510461SAndreas.Sandberg@ARM.com for i,c in enumerate(self.controllers[0:len(self.sequencers)]): 8610461SAndreas.Sandberg@ARM.com c.sequencer = self.sequencers[i] 8710461SAndreas.Sandberg@ARM.com 8810461SAndreas.Sandberg@ARM.com self.num_of_sequencers = len(self.sequencers) 8910461SAndreas.Sandberg@ARM.com 9010461SAndreas.Sandberg@ARM.com # Create the network and connect the controllers. 9110461SAndreas.Sandberg@ARM.com # NOTE: This is quite different if using Garnet! 9210461SAndreas.Sandberg@ARM.com self.network.connectControllers(self.controllers) 9310461SAndreas.Sandberg@ARM.com self.network.setup_buffers() 9410461SAndreas.Sandberg@ARM.com 9510461SAndreas.Sandberg@ARM.com # Set up a proxy port for the system_port. Used for load binaries and 9610461SAndreas.Sandberg@ARM.com # other functional-only things. 9710461SAndreas.Sandberg@ARM.com self.sys_port_proxy = RubyPortProxy() 9810461SAndreas.Sandberg@ARM.com system.system_port = self.sys_port_proxy.slave 9911168Sandreas.hansson@arm.com 10011168Sandreas.hansson@arm.com # Connect up the sequencers to the random tester 10110461SAndreas.Sandberg@ARM.com for seq in self.sequencers: 10211168Sandreas.hansson@arm.com if seq.support_data_reqs and seq.support_inst_reqs: 10310461SAndreas.Sandberg@ARM.com tester.cpuInstDataPort = seq.slave 10410461SAndreas.Sandberg@ARM.com elif seq.support_data_reqs: 10510461SAndreas.Sandberg@ARM.com tester.cpuDataPort = seq.slave 10610461SAndreas.Sandberg@ARM.com elif seq.support_inst_reqs: 10710461SAndreas.Sandberg@ARM.com tester.cpuInstDataPort = seq.slave 10810461SAndreas.Sandberg@ARM.com 10910461SAndreas.Sandberg@ARM.com # Do not automatically retry stalled Ruby requests 11010461SAndreas.Sandberg@ARM.com seq.no_retry_on_stall = True 11110461SAndreas.Sandberg@ARM.com 11211168Sandreas.hansson@arm.com # Tell each sequencer this is the ruby tester so that it 11310461SAndreas.Sandberg@ARM.com # copies the subblock back to the checker 11410461SAndreas.Sandberg@ARM.com seq.using_ruby_tester = True 11510461SAndreas.Sandberg@ARM.com