simple_cache.py revision 12339
1# -*- coding: utf-8 -*- 2# Copyright (c) 2017 Jason Lowe-Power 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Jason Lowe-Power 29 30""" This file creates a barebones system and executes 'hello', a simple Hello 31World application. Adds a simple cache between the CPU and the membus. 32 33This config file assumes that the x86 ISA was built. 34""" 35 36# import the m5 (gem5) library created when gem5 is built 37import m5 38# import all of the SimObjects 39from m5.objects import * 40 41# create the system we are going to simulate 42system = System() 43 44# Set the clock fequency of the system (and all of its children) 45system.clk_domain = SrcClockDomain() 46system.clk_domain.clock = '1GHz' 47system.clk_domain.voltage_domain = VoltageDomain() 48 49# Set up the system 50system.mem_mode = 'timing' # Use timing accesses 51system.mem_ranges = [AddrRange('512MB')] # Create an address range 52 53# Create a simple CPU 54system.cpu = TimingSimpleCPU() 55 56# Create a memory bus, a coherent crossbar, in this case 57system.membus = SystemXBar() 58 59# Create a simple cache 60system.cache = SimpleCache(size='1kB') 61 62# Connect the I and D cache ports of the CPU to the memobj. 63# Since cpu_side is a vector port, each time one of these is connected, it will 64# create a new instance of the CPUSidePort class 65system.cpu.icache_port = system.cache.cpu_side 66system.cpu.dcache_port = system.cache.cpu_side 67 68# Hook the cache up to the memory bus 69system.cache.mem_side = system.membus.slave 70 71# create the interrupt controller for the CPU and connect to the membus 72system.cpu.createInterruptController() 73system.cpu.interrupts[0].pio = system.membus.master 74system.cpu.interrupts[0].int_master = system.membus.slave 75system.cpu.interrupts[0].int_slave = system.membus.master 76 77# Create a DDR3 memory controller and connect it to the membus 78system.mem_ctrl = DDR3_1600_8x8() 79system.mem_ctrl.range = system.mem_ranges[0] 80system.mem_ctrl.port = system.membus.master 81 82# Connect the system up to the membus 83system.system_port = system.membus.slave 84 85# Create a process for a simple "Hello World" application 86process = Process() 87# Set the command 88# cmd is a list which begins with the executable (like argv) 89process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello'] 90# Set the cpu to use the process as its workload and create thread contexts 91system.cpu.workload = process 92system.cpu.createThreads() 93 94# set up the root SimObject and start the simulation 95root = Root(full_system = False, system = system) 96# instantiate all of the objects we've created above 97m5.instantiate() 98 99print "Beginning simulation!" 100exit_event = m5.simulate() 101print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) 102