two_level.py revision 11154
111104Spower.jg@gmail.com# -*- coding: utf-8 -*- 211104Spower.jg@gmail.com# Copyright (c) 2015 Jason Power 311104Spower.jg@gmail.com# All rights reserved. 411104Spower.jg@gmail.com# 511104Spower.jg@gmail.com# Redistribution and use in source and binary forms, with or without 611104Spower.jg@gmail.com# modification, are permitted provided that the following conditions are 711104Spower.jg@gmail.com# met: redistributions of source code must retain the above copyright 811104Spower.jg@gmail.com# notice, this list of conditions and the following disclaimer; 911104Spower.jg@gmail.com# redistributions in binary form must reproduce the above copyright 1011104Spower.jg@gmail.com# notice, this list of conditions and the following disclaimer in the 1111104Spower.jg@gmail.com# documentation and/or other materials provided with the distribution; 1211104Spower.jg@gmail.com# neither the name of the copyright holders nor the names of its 1311104Spower.jg@gmail.com# contributors may be used to endorse or promote products derived from 1411104Spower.jg@gmail.com# this software without specific prior written permission. 1511104Spower.jg@gmail.com# 1611104Spower.jg@gmail.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711104Spower.jg@gmail.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811104Spower.jg@gmail.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911104Spower.jg@gmail.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011104Spower.jg@gmail.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111104Spower.jg@gmail.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211104Spower.jg@gmail.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311104Spower.jg@gmail.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411104Spower.jg@gmail.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511104Spower.jg@gmail.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611104Spower.jg@gmail.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711104Spower.jg@gmail.com# 2811104Spower.jg@gmail.com# Authors: Jason Power 2911104Spower.jg@gmail.com 3011104Spower.jg@gmail.com""" This file creates a single CPU and a two-level cache system. 3111104Spower.jg@gmail.comThis script takes a single parameter which specifies a binary to execute. 3211104Spower.jg@gmail.comIf none is provided it executes 'hello' by default (mostly used for testing) 3311104Spower.jg@gmail.com 3411104Spower.jg@gmail.comSee Part 1, Chapter 3: Adding cache to the configuration script in the 3511104Spower.jg@gmail.comlearning_gem5 book for more information about this script. 3611104Spower.jg@gmail.comThis file exports options for the L1 I/D and L2 cache sizes. 3711104Spower.jg@gmail.com 3811104Spower.jg@gmail.comIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 3911104Spower.jg@gmail.com also needs to be updated. For now, email Jason <power.jg@gmail.com> 4011104Spower.jg@gmail.com 4111104Spower.jg@gmail.com""" 4211104Spower.jg@gmail.com 4311104Spower.jg@gmail.com# import the m5 (gem5) library created when gem5 is built 4411104Spower.jg@gmail.comimport m5 4511104Spower.jg@gmail.com# import all of the SimObjects 4611104Spower.jg@gmail.comfrom m5.objects import * 4711104Spower.jg@gmail.com 4811104Spower.jg@gmail.com# Add the common scripts to our path 4911104Spower.jg@gmail.comm5.util.addToPath('../../common') 5011104Spower.jg@gmail.com 5111104Spower.jg@gmail.com# import the caches which we made 5211104Spower.jg@gmail.comfrom caches import * 5311104Spower.jg@gmail.com 5411104Spower.jg@gmail.com# import the SimpleOpts module 5511104Spower.jg@gmail.comimport SimpleOpts 5611104Spower.jg@gmail.com 5711104Spower.jg@gmail.com# Set the usage message to display 5811104Spower.jg@gmail.comSimpleOpts.set_usage("usage: %prog [options] <binary to execute>") 5911104Spower.jg@gmail.com 6011104Spower.jg@gmail.com# Finalize the arguments and grab the opts so we can pass it on to our objects 6111104Spower.jg@gmail.com(opts, args) = SimpleOpts.parse_args() 6211104Spower.jg@gmail.com 6311104Spower.jg@gmail.com# get ISA for the default binary to run. This is mostly for simple testing 6411104Spower.jg@gmail.comisa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 6511104Spower.jg@gmail.com 6611104Spower.jg@gmail.com# Default to running 'hello', use the compiled ISA to find the binary 6711104Spower.jg@gmail.combinary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello' 6811104Spower.jg@gmail.com 6911104Spower.jg@gmail.com# Check if there was a binary passed in via the command line and error if 7011104Spower.jg@gmail.com# there are too many arguments 7111104Spower.jg@gmail.comif len(args) == 1: 7211104Spower.jg@gmail.com binary = args[0] 7311104Spower.jg@gmail.comelif len(args) > 1: 7411104Spower.jg@gmail.com SimpleOpts.print_help() 7511104Spower.jg@gmail.com m5.fatal("Expected a binary to execute as positional argument") 7611104Spower.jg@gmail.com 7711104Spower.jg@gmail.com# create the system we are going to simulate 7811104Spower.jg@gmail.comsystem = System() 7911104Spower.jg@gmail.com 8011104Spower.jg@gmail.com# Set the clock fequency of the system (and all of its children) 8111104Spower.jg@gmail.comsystem.clk_domain = SrcClockDomain() 8211104Spower.jg@gmail.comsystem.clk_domain.clock = '1GHz' 8311104Spower.jg@gmail.comsystem.clk_domain.voltage_domain = VoltageDomain() 8411104Spower.jg@gmail.com 8511104Spower.jg@gmail.com# Set up the system 8611104Spower.jg@gmail.comsystem.mem_mode = 'timing' # Use timing accesses 8711104Spower.jg@gmail.comsystem.mem_ranges = [AddrRange('512MB')] # Create an address range 8811104Spower.jg@gmail.com 8911104Spower.jg@gmail.com# Create a simple CPU 9011104Spower.jg@gmail.comsystem.cpu = TimingSimpleCPU() 9111104Spower.jg@gmail.com 9211104Spower.jg@gmail.com# Create an L1 instruction and data cache 9311104Spower.jg@gmail.comsystem.cpu.icache = L1ICache(opts) 9411104Spower.jg@gmail.comsystem.cpu.dcache = L1DCache(opts) 9511104Spower.jg@gmail.com 9611104Spower.jg@gmail.com# Connect the instruction and data caches to the CPU 9711104Spower.jg@gmail.comsystem.cpu.icache.connectCPU(system.cpu) 9811104Spower.jg@gmail.comsystem.cpu.dcache.connectCPU(system.cpu) 9911104Spower.jg@gmail.com 10011104Spower.jg@gmail.com# Create a memory bus, a coherent crossbar, in this case 10111104Spower.jg@gmail.comsystem.l2bus = L2XBar() 10211104Spower.jg@gmail.com 10311104Spower.jg@gmail.com# Hook the CPU ports up to the l2bus 10411104Spower.jg@gmail.comsystem.cpu.icache.connectBus(system.l2bus) 10511104Spower.jg@gmail.comsystem.cpu.dcache.connectBus(system.l2bus) 10611104Spower.jg@gmail.com 10711104Spower.jg@gmail.com# Create an L2 cache and connect it to the l2bus 10811104Spower.jg@gmail.comsystem.l2cache = L2Cache(opts) 10911104Spower.jg@gmail.comsystem.l2cache.connectCPUSideBus(system.l2bus) 11011104Spower.jg@gmail.com 11111104Spower.jg@gmail.com# Create a memory bus 11211104Spower.jg@gmail.comsystem.membus = SystemXBar() 11311104Spower.jg@gmail.com 11411104Spower.jg@gmail.com# Connect the L2 cache to the membus 11511104Spower.jg@gmail.comsystem.l2cache.connectMemSideBus(system.membus) 11611104Spower.jg@gmail.com 11711104Spower.jg@gmail.com# create the interrupt controller for the CPU 11811104Spower.jg@gmail.comsystem.cpu.createInterruptController() 11911104Spower.jg@gmail.com 12011104Spower.jg@gmail.com# For x86 only, make sure the interrupts are connected to the memory 12111104Spower.jg@gmail.com# Note: these are directly connected to the memory bus and are not cached 12211104Spower.jg@gmail.comif m5.defines.buildEnv['TARGET_ISA'] == "x86": 12311154Sandreas.hansson@arm.com system.cpu.interrupts[0].pio = system.membus.master 12411154Sandreas.hansson@arm.com system.cpu.interrupts[0].int_master = system.membus.slave 12511154Sandreas.hansson@arm.com system.cpu.interrupts[0].int_slave = system.membus.master 12611104Spower.jg@gmail.com 12711104Spower.jg@gmail.com# Connect the system up to the membus 12811104Spower.jg@gmail.comsystem.system_port = system.membus.slave 12911104Spower.jg@gmail.com 13011104Spower.jg@gmail.com# Create a DDR3 memory controller 13111104Spower.jg@gmail.comsystem.mem_ctrl = DDR3_1600_x64() 13211104Spower.jg@gmail.comsystem.mem_ctrl.range = system.mem_ranges[0] 13311104Spower.jg@gmail.comsystem.mem_ctrl.port = system.membus.master 13411104Spower.jg@gmail.com 13511104Spower.jg@gmail.com# Create a process for a simple "Hello World" application 13611104Spower.jg@gmail.comprocess = LiveProcess() 13711104Spower.jg@gmail.com# Set the command 13811104Spower.jg@gmail.com# cmd is a list which begins with the executable (like argv) 13911104Spower.jg@gmail.comprocess.cmd = [binary] 14011104Spower.jg@gmail.com# Set the cpu to use the process as its workload and create thread contexts 14111104Spower.jg@gmail.comsystem.cpu.workload = process 14211104Spower.jg@gmail.comsystem.cpu.createThreads() 14311104Spower.jg@gmail.com 14411104Spower.jg@gmail.com# set up the root SimObject and start the simulation 14511104Spower.jg@gmail.comroot = Root(full_system = False, system = system) 14611104Spower.jg@gmail.com# instantiate all of the objects we've created above 14711104Spower.jg@gmail.comm5.instantiate() 14811104Spower.jg@gmail.com 14911104Spower.jg@gmail.comprint "Beginning simulation!" 15011104Spower.jg@gmail.comexit_event = m5.simulate() 15111104Spower.jg@gmail.comprint 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) 152