se.py revision 9665 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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11# modified or unmodified, in source code or in binary form.
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13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47
48import m5
49from m5.defines import buildEnv
50from m5.objects import *
51from m5.util import addToPath, fatal
52
53addToPath('../common')
54addToPath('../ruby')
55addToPath('../topologies')
56
57import Options
58import Ruby
59import Simulation
60import CacheConfig
61from Caches import *
62from cpu2000 import *
63
64def get_processes(options):
65    """Interprets provided options and returns a list of processes"""
66
67    multiprocesses = []
68    inputs = []
69    outputs = []
70    errouts = []
71    pargs = []
72
73    workloads = options.cmd.split(';')
74    if options.input != "":
75        inputs = options.input.split(';')
76    if options.output != "":
77        outputs = options.output.split(';')
78    if options.errout != "":
79        errouts = options.errout.split(';')
80    if options.options != "":
81        pargs = options.options.split(';')
82
83    idx = 0
84    for wrkld in workloads:
85        process = LiveProcess()
86        process.executable = wrkld
87
88        if len(pargs) > idx:
89            process.cmd = [wrkld] + pargs[idx].split()
90        else:
91            process.cmd = [wrkld]
92
93        if len(inputs) > idx:
94            process.input = inputs[idx]
95        if len(outputs) > idx:
96            process.output = outputs[idx]
97        if len(errouts) > idx:
98            process.errout = errouts[idx]
99
100        multiprocesses.append(process)
101        idx += 1
102
103    if options.smt:
104        assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
105        return multiprocesses, idx
106    else:
107        return multiprocesses, 1
108
109
110parser = optparse.OptionParser()
111Options.addCommonOptions(parser)
112Options.addSEOptions(parser)
113
114if '--ruby' in sys.argv:
115    Ruby.define_options(parser)
116
117(options, args) = parser.parse_args()
118
119if args:
120    print "Error: script doesn't take any positional arguments"
121    sys.exit(1)
122
123multiprocesses = []
124numThreads = 1
125
126if options.bench:
127    apps = options.bench.split("-")
128    if len(apps) != options.num_cpus:
129        print "number of benchmarks not equal to set num_cpus!"
130        sys.exit(1)
131
132    for app in apps:
133        try:
134            if buildEnv['TARGET_ISA'] == 'alpha':
135                exec("workload = %s('alpha', 'tru64', 'ref')" % app)
136            else:
137                exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
138            multiprocesses.append(workload.makeLiveProcess())
139        except:
140            print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
141            sys.exit(1)
142elif options.cmd:
143    multiprocesses, numThreads = get_processes(options)
144else:
145    print >> sys.stderr, "No workload specified. Exiting!\n"
146    sys.exit(1)
147
148
149(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
150CPUClass.clock = options.clock
151CPUClass.numThreads = numThreads
152
153MemClass = Simulation.setMemClass(options)
154
155# Check -- do not allow SMT with multiple CPUs
156if options.smt and options.num_cpus > 1:
157    fatal("You cannot use SMT with multiple CPUs!")
158
159np = options.num_cpus
160system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
161                physmem = MemClass(range=AddrRange("512MB")),
162                membus = CoherentBus(), mem_mode = test_mem_mode)
163
164# Sanity check
165if options.fastmem:
166    if CPUClass != AtomicSimpleCPU:
167        fatal("Fastmem can only be used with atomic CPU!")
168    if (options.caches or options.l2cache):
169        fatal("You cannot use fastmem in combination with caches!")
170
171if options.simpoint_profile:
172    if not options.fastmem:
173        # Atomic CPU checked with fastmem option already
174        fatal("SimPoint generation should be done with atomic cpu and fastmem")
175    if np > 1:
176        fatal("SimPoint generation not supported with more than one CPUs")
177
178for i in xrange(np):
179    if options.smt:
180        system.cpu[i].workload = multiprocesses
181    elif len(multiprocesses) == 1:
182        system.cpu[i].workload = multiprocesses[0]
183    else:
184        system.cpu[i].workload = multiprocesses[i]
185
186    if options.fastmem:
187        system.cpu[i].fastmem = True
188
189    if options.simpoint_profile:
190        system.cpu[i].simpoint_profile = True
191        system.cpu[i].simpoint_interval = options.simpoint_interval
192
193    if options.checker:
194        system.cpu[i].addCheckerCpu()
195
196    system.cpu[i].createThreads()
197
198if options.ruby:
199    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
200        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
201        sys.exit(1)
202
203    # Set the option for physmem so that it is not allocated any space
204    system.physmem.null = True
205
206    options.use_map = True
207    Ruby.create_system(options, system)
208    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
209
210    for i in xrange(np):
211        ruby_port = system.ruby._cpu_ruby_ports[i]
212
213        # Create the interrupt controller and connect its ports to Ruby
214        # Note that the interrupt controller is always present but only
215        # in x86 does it have message ports that need to be connected
216        system.cpu[i].createInterruptController()
217
218        # Connect the cpu's cache ports to Ruby
219        system.cpu[i].icache_port = ruby_port.slave
220        system.cpu[i].dcache_port = ruby_port.slave
221        if buildEnv['TARGET_ISA'] == 'x86':
222            system.cpu[i].interrupts.pio = ruby_port.master
223            system.cpu[i].interrupts.int_master = ruby_port.slave
224            system.cpu[i].interrupts.int_slave = ruby_port.master
225            system.cpu[i].itb.walker.port = ruby_port.slave
226            system.cpu[i].dtb.walker.port = ruby_port.slave
227else:
228    system.system_port = system.membus.slave
229    system.physmem.port = system.membus.master
230    CacheConfig.config_cache(options, system)
231
232root = Root(full_system = False, system = system)
233Simulation.run(options, root, system, FutureClass)
234