se.py revision 9129:b57966a6c512
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2008 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Steve Reinhardt 40 41# Simple test script 42# 43# "m5 test.py" 44 45import optparse 46import sys 47 48import m5 49from m5.defines import buildEnv 50from m5.objects import * 51from m5.util import addToPath, fatal 52 53addToPath('../common') 54addToPath('../ruby') 55addToPath('../topologies') 56 57import Options 58import Ruby 59import Simulation 60import CacheConfig 61from Caches import * 62from cpu2000 import * 63 64parser = optparse.OptionParser() 65Options.addCommonOptions(parser) 66Options.addSEOptions(parser) 67 68if '--ruby' in sys.argv: 69 Ruby.define_options(parser) 70 71(options, args) = parser.parse_args() 72 73if args: 74 print "Error: script doesn't take any positional arguments" 75 sys.exit(1) 76 77multiprocesses = [] 78apps = [] 79 80if options.bench: 81 apps = options.bench.split("-") 82 if len(apps) != options.num_cpus: 83 print "number of benchmarks not equal to set num_cpus!" 84 sys.exit(1) 85 86 for app in apps: 87 try: 88 if buildEnv['TARGET_ISA'] == 'alpha': 89 exec("workload = %s('alpha', 'tru64', 'ref')" % app) 90 else: 91 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app) 92 multiprocesses.append(workload.makeLiveProcess()) 93 except: 94 print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) 95 sys.exit(1) 96elif options.cmd: 97 process = LiveProcess() 98 process.executable = options.cmd 99 process.cmd = [options.cmd] + options.options.split() 100 multiprocesses.append(process) 101else: 102 print >> sys.stderr, "No workload specified. Exiting!\n" 103 sys.exit(1) 104 105 106if options.input != "": 107 process.input = options.input 108if options.output != "": 109 process.output = options.output 110if options.errout != "": 111 process.errout = options.errout 112 113 114# By default, set workload to path of user-specified binary 115workloads = options.cmd 116numThreads = 1 117 118if options.cpu_type == "detailed" or options.cpu_type == "inorder": 119 #check for SMT workload 120 workloads = options.cmd.split(';') 121 if len(workloads) > 1: 122 process = [] 123 smt_idx = 0 124 inputs = [] 125 outputs = [] 126 errouts = [] 127 128 if options.input != "": 129 inputs = options.input.split(';') 130 if options.output != "": 131 outputs = options.output.split(';') 132 if options.errout != "": 133 errouts = options.errout.split(';') 134 135 for wrkld in workloads: 136 smt_process = LiveProcess() 137 smt_process.executable = wrkld 138 smt_process.cmd = wrkld + " " + options.options 139 if inputs and inputs[smt_idx]: 140 smt_process.input = inputs[smt_idx] 141 if outputs and outputs[smt_idx]: 142 smt_process.output = outputs[smt_idx] 143 if errouts and errouts[smt_idx]: 144 smt_process.errout = errouts[smt_idx] 145 process += [smt_process, ] 146 smt_idx += 1 147 numThreads = len(workloads) 148 149(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 150CPUClass.clock = options.clock 151CPUClass.numThreads = numThreads; 152 153np = options.num_cpus 154 155system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 156 physmem = SimpleMemory(range=AddrRange("512MB")), 157 membus = CoherentBus(), mem_mode = test_mem_mode) 158 159# Sanity check 160if options.fastmem and (options.caches or options.l2cache): 161 fatal("You cannot use fastmem in combination with caches!") 162 163for i in xrange(np): 164 if len(multiprocesses) == 1: 165 system.cpu[i].workload = multiprocesses[0] 166 else: 167 system.cpu[i].workload = multiprocesses[i] 168 169 if options.fastmem: 170 system.cpu[i].fastmem = True 171 172 if options.checker: 173 system.cpu[i].addCheckerCpu() 174 175if options.ruby: 176 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 177 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 178 sys.exit(1) 179 180 options.use_map = True 181 Ruby.create_system(options, system) 182 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 183 184 for i in xrange(np): 185 ruby_port = system.ruby._cpu_ruby_ports[i] 186 187 # Create the interrupt controller and connect its ports to Ruby 188 system.cpu[i].createInterruptController() 189 system.cpu[i].interrupts.pio = ruby_port.master 190 system.cpu[i].interrupts.int_master = ruby_port.slave 191 system.cpu[i].interrupts.int_slave = ruby_port.master 192 193 # Connect the cpu's cache ports to Ruby 194 system.cpu[i].icache_port = ruby_port.slave 195 system.cpu[i].dcache_port = ruby_port.slave 196else: 197 system.system_port = system.membus.slave 198 system.physmem.port = system.membus.master 199 CacheConfig.config_cache(options, system) 200 201root = Root(full_system = False, system = system) 202Simulation.run(options, root, system, FutureClass) 203