se.py revision 8839
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2008 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Steve Reinhardt 40 41# Simple test script 42# 43# "m5 test.py" 44 45import os 46import optparse 47import sys 48from os.path import join as joinpath 49 50import m5 51from m5.defines import buildEnv 52from m5.objects import * 53from m5.util import addToPath, fatal 54 55addToPath('../common') 56addToPath('../ruby') 57 58import Ruby 59 60import Simulation 61import CacheConfig 62from Caches import * 63from cpu2000 import * 64 65# Get paths we might need. It's expected this file is in m5/configs/example. 66config_path = os.path.dirname(os.path.abspath(__file__)) 67config_root = os.path.dirname(config_path) 68m5_root = os.path.dirname(config_root) 69 70parser = optparse.OptionParser() 71 72# Benchmark options 73parser.add_option("-c", "--cmd", 74 default=joinpath(m5_root, "tests/test-progs/hello/bin/%s/linux/hello" % \ 75 buildEnv['TARGET_ISA']), 76 help="The binary to run in syscall emulation mode.") 77parser.add_option("-o", "--options", default="", 78 help='The options to pass to the binary, use " " around the entire string') 79parser.add_option("-i", "--input", default="", help="Read stdin from a file.") 80parser.add_option("--output", default="", help="Redirect stdout to a file.") 81parser.add_option("--errout", default="", help="Redirect stderr to a file.") 82 83execfile(os.path.join(config_root, "common", "Options.py")) 84 85if buildEnv['PROTOCOL'] != 'None': 86 parser.add_option("--ruby", action="store_true") 87 if '--ruby' in sys.argv: 88 Ruby.define_options(parser) 89 90(options, args) = parser.parse_args() 91 92if args: 93 print "Error: script doesn't take any positional arguments" 94 sys.exit(1) 95 96multiprocesses = [] 97apps = [] 98 99if options.bench: 100 apps = options.bench.split("-") 101 if len(apps) != options.num_cpus: 102 print "number of benchmarks not equal to set num_cpus!" 103 sys.exit(1) 104 105 for app in apps: 106 try: 107 if buildEnv['TARGET_ISA'] == 'alpha': 108 exec("workload = %s('alpha', 'tru64', 'ref')" % app) 109 else: 110 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app) 111 multiprocesses.append(workload.makeLiveProcess()) 112 except: 113 print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) 114 sys.exit(1) 115else: 116 process = LiveProcess() 117 process.executable = options.cmd 118 process.cmd = [options.cmd] + options.options.split() 119 multiprocesses.append(process) 120 121 122if options.input != "": 123 process.input = options.input 124if options.output != "": 125 process.output = options.output 126if options.errout != "": 127 process.errout = options.errout 128 129 130# By default, set workload to path of user-specified binary 131workloads = options.cmd 132numThreads = 1 133 134if options.cpu_type == "detailed" or options.cpu_type == "inorder": 135 #check for SMT workload 136 workloads = options.cmd.split(';') 137 if len(workloads) > 1: 138 process = [] 139 smt_idx = 0 140 inputs = [] 141 outputs = [] 142 errouts = [] 143 144 if options.input != "": 145 inputs = options.input.split(';') 146 if options.output != "": 147 outputs = options.output.split(';') 148 if options.errout != "": 149 errouts = options.errout.split(';') 150 151 for wrkld in workloads: 152 smt_process = LiveProcess() 153 smt_process.executable = wrkld 154 smt_process.cmd = wrkld + " " + options.options 155 if inputs and inputs[smt_idx]: 156 smt_process.input = inputs[smt_idx] 157 if outputs and outputs[smt_idx]: 158 smt_process.output = outputs[smt_idx] 159 if errouts and errouts[smt_idx]: 160 smt_process.errout = errouts[smt_idx] 161 process += [smt_process, ] 162 smt_idx += 1 163 numThreads = len(workloads) 164 165if options.ruby: 166 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 167 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 168 sys.exit(1) 169 170(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 171CPUClass.clock = '2GHz' 172CPUClass.numThreads = numThreads; 173 174np = options.num_cpus 175 176system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 177 physmem = PhysicalMemory(range=AddrRange("512MB")), 178 membus = Bus(), mem_mode = test_mem_mode) 179 180if options.ruby: 181 options.use_map = True 182 Ruby.create_system(options, system) 183 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 184else: 185 system.system_port = system.membus.slave 186 system.physmem.port = system.membus.master 187 CacheConfig.config_cache(options, system) 188 189for i in xrange(np): 190 system.cpu[i].workload = multiprocesses[i] 191 192 if options.ruby: 193 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port 194 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port 195 196 if options.fastmem: 197 system.cpu[0].physmem_port = system.physmem.port 198 199root = Root(full_system = False, system = system) 200 201Simulation.run(options, root, system, FutureClass) 202