se.py revision 6642:0b72f4f7c814 
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29# Simple test script
30#
31# "m5 test.py"
32
33import m5
34
35if m5.build_env['FULL_SYSTEM']:
36    m5.fatal("This script requires syscall emulation mode (*_SE).")
37
38from m5.objects import *
39import os, optparse, sys
40from os.path import join as joinpath
41m5.AddToPath('../common')
42import Simulation
43from Caches import *
44from cpu2000 import *
45
46# Get paths we might need.  It's expected this file is in m5/configs/example.
47config_path = os.path.dirname(os.path.abspath(__file__))
48config_root = os.path.dirname(config_path)
49m5_root = os.path.dirname(config_root)
50
51parser = optparse.OptionParser()
52
53# Benchmark options
54parser.add_option("-c", "--cmd",
55    default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
56    help="The binary to run in syscall emulation mode.")
57parser.add_option("-o", "--options", default="",
58    help='The options to pass to the binary, use " " around the entire string')
59parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
60parser.add_option("--output", default="", help="Redirect stdout to a file.")
61parser.add_option("--errout", default="", help="Redirect stderr to a file.")
62
63execfile(os.path.join(config_root, "common", "Options.py"))
64
65(options, args) = parser.parse_args()
66
67if args:
68    print "Error: script doesn't take any positional arguments"
69    sys.exit(1)
70
71if options.bench:
72    try:
73        if m5.build_env['TARGET_ISA'] != 'alpha':
74            print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
75            sys.exit(1)
76        exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
77        process = workload.makeLiveProcess()
78    except:
79        print >>sys.stderr, "Unable to find workload for %s" % options.bench
80        sys.exit(1)
81else:
82    process = LiveProcess()
83    process.executable = options.cmd
84    process.cmd = [options.cmd] + options.options.split()
85
86
87if options.input != "":
88    process.input = options.input
89if options.output != "":
90    process.output = options.output
91if options.errout != "":
92    process.errout = options.errout
93
94
95# By default, set workload to path of user-specified binary
96workloads = options.cmd
97numThreads = 1
98
99if options.detailed or options.inorder:
100    #check for SMT workload
101    workloads = options.cmd.split(';')
102    if len(workloads) > 1:
103        process = []
104        smt_idx = 0
105        inputs = []
106        outputs = []
107        errouts = []
108
109        if options.input != "":
110            inputs = options.input.split(';')
111        if options.output != "":
112            outputs = options.output.split(';')
113        if options.errout != "":
114            errouts = options.errout.split(';')
115
116        for wrkld in workloads:
117            smt_process = LiveProcess()
118            smt_process.executable = wrkld
119            smt_process.cmd = wrkld + " " + options.options
120            if inputs and inputs[smt_idx]:
121                smt_process.input = inputs[smt_idx]
122            if outputs and outputs[smt_idx]:
123                smt_process.output = outputs[smt_idx]
124            if errouts and errouts[smt_idx]:
125                smt_process.errout = errouts[smt_idx]
126            process += [smt_process, ]
127            smt_idx += 1
128    numThreads = len(workloads)
129
130(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
131
132CPUClass.clock = '2GHz'
133CPUClass.numThreads = numThreads;
134
135np = options.num_cpus
136
137system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
138                physmem = PhysicalMemory(range=AddrRange("512MB")),
139                membus = Bus(), mem_mode = test_mem_mode)
140
141system.physmem.port = system.membus.port
142
143if options.l2cache:
144    system.l2 = L2Cache(size='2MB')
145    system.tol2bus = Bus()
146    system.l2.cpu_side = system.tol2bus.port
147    system.l2.mem_side = system.membus.port
148
149for i in xrange(np):
150    if options.caches:
151        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
152                                              L1Cache(size = '64kB'))
153    if options.l2cache:
154        system.cpu[i].connectMemPorts(system.tol2bus)
155    else:
156        system.cpu[i].connectMemPorts(system.membus)
157    system.cpu[i].workload = process
158
159    if options.fastmem:
160        system.cpu[0].physmem_port = system.physmem.port
161
162root = Root(system = system)
163
164Simulation.run(options, root, system, FutureClass)
165