se.py revision 12941:24771c7aee2e 
1# Copyright (c) 2012-2013 ARM Limited
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13# Copyright (c) 2006-2008 The Regents of The University of Michigan
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45from __future__ import print_function
46
47import optparse
48import sys
49import os
50
51import m5
52from m5.defines import buildEnv
53from m5.objects import *
54from m5.util import addToPath, fatal, warn
55
56addToPath('../')
57
58from ruby import Ruby
59
60from common import Options
61from common import Simulation
62from common import CacheConfig
63from common import CpuConfig
64from common import MemConfig
65from common.Caches import *
66from common.cpu2000 import *
67
68def get_processes(options):
69    """Interprets provided options and returns a list of processes"""
70
71    multiprocesses = []
72    inputs = []
73    outputs = []
74    errouts = []
75    pargs = []
76
77    workloads = options.cmd.split(';')
78    if options.input != "":
79        inputs = options.input.split(';')
80    if options.output != "":
81        outputs = options.output.split(';')
82    if options.errout != "":
83        errouts = options.errout.split(';')
84    if options.options != "":
85        pargs = options.options.split(';')
86
87    idx = 0
88    for wrkld in workloads:
89        process = Process(pid = 100 + idx)
90        process.executable = wrkld
91        process.cwd = os.getcwd()
92
93        if options.env:
94            with open(options.env, 'r') as f:
95                process.env = [line.rstrip() for line in f]
96
97        if len(pargs) > idx:
98            process.cmd = [wrkld] + pargs[idx].split()
99        else:
100            process.cmd = [wrkld]
101
102        if len(inputs) > idx:
103            process.input = inputs[idx]
104        if len(outputs) > idx:
105            process.output = outputs[idx]
106        if len(errouts) > idx:
107            process.errout = errouts[idx]
108
109        multiprocesses.append(process)
110        idx += 1
111
112    if options.smt:
113        assert(options.cpu_type == "DerivO3CPU")
114        return multiprocesses, idx
115    else:
116        return multiprocesses, 1
117
118
119parser = optparse.OptionParser()
120Options.addCommonOptions(parser)
121Options.addSEOptions(parser)
122
123if '--ruby' in sys.argv:
124    Ruby.define_options(parser)
125
126(options, args) = parser.parse_args()
127
128if args:
129    print("Error: script doesn't take any positional arguments")
130    sys.exit(1)
131
132multiprocesses = []
133numThreads = 1
134
135if options.bench:
136    apps = options.bench.split("-")
137    if len(apps) != options.num_cpus:
138        print("number of benchmarks not equal to set num_cpus!")
139        sys.exit(1)
140
141    for app in apps:
142        try:
143            if buildEnv['TARGET_ISA'] == 'alpha':
144                exec("workload = %s('alpha', 'tru64', '%s')" % (
145                        app, options.spec_input))
146            elif buildEnv['TARGET_ISA'] == 'arm':
147                exec("workload = %s('arm_%s', 'linux', '%s')" % (
148                        app, options.arm_iset, options.spec_input))
149            else:
150                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
151                        app, options.spec_input))
152            multiprocesses.append(workload.makeProcess())
153        except:
154            print("Unable to find workload for %s: %s" %
155                  (buildEnv['TARGET_ISA'], app),
156                  file=sys.stderr)
157            sys.exit(1)
158elif options.cmd:
159    multiprocesses, numThreads = get_processes(options)
160else:
161    print("No workload specified. Exiting!\n", file=sys.stderr)
162    sys.exit(1)
163
164
165(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
166CPUClass.numThreads = numThreads
167
168# Check -- do not allow SMT with multiple CPUs
169if options.smt and options.num_cpus > 1:
170    fatal("You cannot use SMT with multiple CPUs!")
171
172np = options.num_cpus
173system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
174                mem_mode = test_mem_mode,
175                mem_ranges = [AddrRange(options.mem_size)],
176                cache_line_size = options.cacheline_size)
177
178if numThreads > 1:
179    system.multi_thread = True
180
181# Create a top-level voltage domain
182system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
183
184# Create a source clock for the system and set the clock period
185system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
186                                   voltage_domain = system.voltage_domain)
187
188# Create a CPU voltage domain
189system.cpu_voltage_domain = VoltageDomain()
190
191# Create a separate clock domain for the CPUs
192system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
193                                       voltage_domain =
194                                       system.cpu_voltage_domain)
195
196# If elastic tracing is enabled, then configure the cpu and attach the elastic
197# trace probe
198if options.elastic_trace_en:
199    CpuConfig.config_etrace(CPUClass, system.cpu, options)
200
201# All cpus belong to a common cpu_clk_domain, therefore running at a common
202# frequency.
203for cpu in system.cpu:
204    cpu.clk_domain = system.cpu_clk_domain
205
206if CpuConfig.is_kvm_cpu(CPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
207    if buildEnv['TARGET_ISA'] == 'x86':
208        system.kvm_vm = KvmVM()
209        for process in multiprocesses:
210            process.useArchPT = True
211            process.kvmInSE = True
212    else:
213        fatal("KvmCPU can only be used in SE mode with x86")
214
215# Sanity check
216if options.fastmem:
217    if CPUClass != AtomicSimpleCPU:
218        fatal("Fastmem can only be used with atomic CPU!")
219    if (options.caches or options.l2cache):
220        fatal("You cannot use fastmem in combination with caches!")
221
222if options.simpoint_profile:
223    if not options.fastmem:
224        # Atomic CPU checked with fastmem option already
225        fatal("SimPoint generation should be done with atomic cpu and fastmem")
226    if np > 1:
227        fatal("SimPoint generation not supported with more than one CPUs")
228
229for i in xrange(np):
230    if options.smt:
231        system.cpu[i].workload = multiprocesses
232    elif len(multiprocesses) == 1:
233        system.cpu[i].workload = multiprocesses[0]
234    else:
235        system.cpu[i].workload = multiprocesses[i]
236
237    if options.fastmem:
238        system.cpu[i].fastmem = True
239
240    if options.simpoint_profile:
241        system.cpu[i].addSimPointProbe(options.simpoint_interval)
242
243    if options.checker:
244        system.cpu[i].addCheckerCpu()
245
246    system.cpu[i].createThreads()
247
248if options.ruby:
249    Ruby.create_system(options, False, system)
250    assert(options.num_cpus == len(system.ruby._cpu_ports))
251
252    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
253                                        voltage_domain = system.voltage_domain)
254    for i in xrange(np):
255        ruby_port = system.ruby._cpu_ports[i]
256
257        # Create the interrupt controller and connect its ports to Ruby
258        # Note that the interrupt controller is always present but only
259        # in x86 does it have message ports that need to be connected
260        system.cpu[i].createInterruptController()
261
262        # Connect the cpu's cache ports to Ruby
263        system.cpu[i].icache_port = ruby_port.slave
264        system.cpu[i].dcache_port = ruby_port.slave
265        if buildEnv['TARGET_ISA'] == 'x86':
266            system.cpu[i].interrupts[0].pio = ruby_port.master
267            system.cpu[i].interrupts[0].int_master = ruby_port.slave
268            system.cpu[i].interrupts[0].int_slave = ruby_port.master
269            system.cpu[i].itb.walker.port = ruby_port.slave
270            system.cpu[i].dtb.walker.port = ruby_port.slave
271else:
272    MemClass = Simulation.setMemClass(options)
273    system.membus = SystemXBar()
274    system.system_port = system.membus.slave
275    CacheConfig.config_cache(options, system)
276    MemConfig.config_mem(options, system)
277
278root = Root(full_system = False, system = system)
279Simulation.run(options, root, system, FutureClass)
280