se.py revision 12564
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2008 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Steve Reinhardt 40 41# Simple test script 42# 43# "m5 test.py" 44 45from __future__ import print_function 46 47import optparse 48import sys 49import os 50 51import m5 52from m5.defines import buildEnv 53from m5.objects import * 54from m5.util import addToPath, fatal, warn 55 56addToPath('../') 57 58from ruby import Ruby 59 60from common import Options 61from common import Simulation 62from common import CacheConfig 63from common import CpuConfig 64from common import MemConfig 65from common.Caches import * 66from common.cpu2000 import * 67 68# Check if KVM support has been enabled, we might need to do VM 69# configuration if that's the case. 70have_kvm_support = 'BaseKvmCPU' in globals() 71def is_kvm_cpu(cpu_class): 72 return have_kvm_support and cpu_class != None and \ 73 issubclass(cpu_class, BaseKvmCPU) 74 75def get_processes(options): 76 """Interprets provided options and returns a list of processes""" 77 78 multiprocesses = [] 79 inputs = [] 80 outputs = [] 81 errouts = [] 82 pargs = [] 83 84 workloads = options.cmd.split(';') 85 if options.input != "": 86 inputs = options.input.split(';') 87 if options.output != "": 88 outputs = options.output.split(';') 89 if options.errout != "": 90 errouts = options.errout.split(';') 91 if options.options != "": 92 pargs = options.options.split(';') 93 94 idx = 0 95 for wrkld in workloads: 96 process = Process(pid = 100 + idx) 97 process.executable = wrkld 98 process.cwd = os.getcwd() 99 100 if options.env: 101 with open(options.env, 'r') as f: 102 process.env = [line.rstrip() for line in f] 103 104 if len(pargs) > idx: 105 process.cmd = [wrkld] + pargs[idx].split() 106 else: 107 process.cmd = [wrkld] 108 109 if len(inputs) > idx: 110 process.input = inputs[idx] 111 if len(outputs) > idx: 112 process.output = outputs[idx] 113 if len(errouts) > idx: 114 process.errout = errouts[idx] 115 116 multiprocesses.append(process) 117 idx += 1 118 119 if options.smt: 120 assert(options.cpu_type == "DerivO3CPU") 121 return multiprocesses, idx 122 else: 123 return multiprocesses, 1 124 125 126parser = optparse.OptionParser() 127Options.addCommonOptions(parser) 128Options.addSEOptions(parser) 129 130if '--ruby' in sys.argv: 131 Ruby.define_options(parser) 132 133(options, args) = parser.parse_args() 134 135if args: 136 print("Error: script doesn't take any positional arguments") 137 sys.exit(1) 138 139multiprocesses = [] 140numThreads = 1 141 142if options.bench: 143 apps = options.bench.split("-") 144 if len(apps) != options.num_cpus: 145 print("number of benchmarks not equal to set num_cpus!") 146 sys.exit(1) 147 148 for app in apps: 149 try: 150 if buildEnv['TARGET_ISA'] == 'alpha': 151 exec("workload = %s('alpha', 'tru64', '%s')" % ( 152 app, options.spec_input)) 153 elif buildEnv['TARGET_ISA'] == 'arm': 154 exec("workload = %s('arm_%s', 'linux', '%s')" % ( 155 app, options.arm_iset, options.spec_input)) 156 else: 157 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 158 app, options.spec_input)) 159 multiprocesses.append(workload.makeProcess()) 160 except: 161 print("Unable to find workload for %s: %s" % 162 (buildEnv['TARGET_ISA'], app), 163 file=sys.stderr) 164 sys.exit(1) 165elif options.cmd: 166 multiprocesses, numThreads = get_processes(options) 167else: 168 print("No workload specified. Exiting!\n", file=sys.stderr) 169 sys.exit(1) 170 171 172(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 173CPUClass.numThreads = numThreads 174 175# Check -- do not allow SMT with multiple CPUs 176if options.smt and options.num_cpus > 1: 177 fatal("You cannot use SMT with multiple CPUs!") 178 179np = options.num_cpus 180system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 181 mem_mode = test_mem_mode, 182 mem_ranges = [AddrRange(options.mem_size)], 183 cache_line_size = options.cacheline_size) 184 185if numThreads > 1: 186 system.multi_thread = True 187 188# Create a top-level voltage domain 189system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 190 191# Create a source clock for the system and set the clock period 192system.clk_domain = SrcClockDomain(clock = options.sys_clock, 193 voltage_domain = system.voltage_domain) 194 195# Create a CPU voltage domain 196system.cpu_voltage_domain = VoltageDomain() 197 198# Create a separate clock domain for the CPUs 199system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 200 voltage_domain = 201 system.cpu_voltage_domain) 202 203# If elastic tracing is enabled, then configure the cpu and attach the elastic 204# trace probe 205if options.elastic_trace_en: 206 CpuConfig.config_etrace(CPUClass, system.cpu, options) 207 208# All cpus belong to a common cpu_clk_domain, therefore running at a common 209# frequency. 210for cpu in system.cpu: 211 cpu.clk_domain = system.cpu_clk_domain 212 213if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass): 214 if buildEnv['TARGET_ISA'] == 'x86': 215 system.kvm_vm = KvmVM() 216 for process in multiprocesses: 217 process.useArchPT = True 218 process.kvmInSE = True 219 else: 220 fatal("KvmCPU can only be used in SE mode with x86") 221 222# Sanity check 223if options.fastmem: 224 if CPUClass != AtomicSimpleCPU: 225 fatal("Fastmem can only be used with atomic CPU!") 226 if (options.caches or options.l2cache): 227 fatal("You cannot use fastmem in combination with caches!") 228 229if options.simpoint_profile: 230 if not options.fastmem: 231 # Atomic CPU checked with fastmem option already 232 fatal("SimPoint generation should be done with atomic cpu and fastmem") 233 if np > 1: 234 fatal("SimPoint generation not supported with more than one CPUs") 235 236for i in xrange(np): 237 if options.smt: 238 system.cpu[i].workload = multiprocesses 239 elif len(multiprocesses) == 1: 240 system.cpu[i].workload = multiprocesses[0] 241 else: 242 system.cpu[i].workload = multiprocesses[i] 243 244 if options.fastmem: 245 system.cpu[i].fastmem = True 246 247 if options.simpoint_profile: 248 system.cpu[i].addSimPointProbe(options.simpoint_interval) 249 250 if options.checker: 251 system.cpu[i].addCheckerCpu() 252 253 system.cpu[i].createThreads() 254 255if options.ruby: 256 Ruby.create_system(options, False, system) 257 assert(options.num_cpus == len(system.ruby._cpu_ports)) 258 259 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 260 voltage_domain = system.voltage_domain) 261 for i in xrange(np): 262 ruby_port = system.ruby._cpu_ports[i] 263 264 # Create the interrupt controller and connect its ports to Ruby 265 # Note that the interrupt controller is always present but only 266 # in x86 does it have message ports that need to be connected 267 system.cpu[i].createInterruptController() 268 269 # Connect the cpu's cache ports to Ruby 270 system.cpu[i].icache_port = ruby_port.slave 271 system.cpu[i].dcache_port = ruby_port.slave 272 if buildEnv['TARGET_ISA'] == 'x86': 273 system.cpu[i].interrupts[0].pio = ruby_port.master 274 system.cpu[i].interrupts[0].int_master = ruby_port.slave 275 system.cpu[i].interrupts[0].int_slave = ruby_port.master 276 system.cpu[i].itb.walker.port = ruby_port.slave 277 system.cpu[i].dtb.walker.port = ruby_port.slave 278else: 279 MemClass = Simulation.setMemClass(options) 280 system.membus = SystemXBar() 281 system.system_port = system.membus.slave 282 CacheConfig.config_cache(options, system) 283 MemConfig.config_mem(options, system) 284 285root = Root(full_system = False, system = system) 286Simulation.run(options, root, system, FutureClass) 287