se.py revision 10720:67b3e74de9ae 
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
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17# modification, are permitted provided that the following conditions are
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47import os
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal
53
54addToPath('../common')
55addToPath('../ruby')
56
57import Options
58import Ruby
59import Simulation
60import CacheConfig
61import MemConfig
62from Caches import *
63from cpu2000 import *
64
65# Check if KVM support has been enabled, we might need to do VM
66# configuration if that's the case.
67have_kvm_support = 'BaseKvmCPU' in globals()
68def is_kvm_cpu(cpu_class):
69    return have_kvm_support and cpu_class != None and \
70        issubclass(cpu_class, BaseKvmCPU)
71
72def get_processes(options):
73    """Interprets provided options and returns a list of processes"""
74
75    multiprocesses = []
76    inputs = []
77    outputs = []
78    errouts = []
79    pargs = []
80
81    workloads = options.cmd.split(';')
82    if options.input != "":
83        inputs = options.input.split(';')
84    if options.output != "":
85        outputs = options.output.split(';')
86    if options.errout != "":
87        errouts = options.errout.split(';')
88    if options.options != "":
89        pargs = options.options.split(';')
90
91    idx = 0
92    for wrkld in workloads:
93        process = LiveProcess()
94        process.executable = wrkld
95        process.cwd = os.getcwd()
96
97        if len(pargs) > idx:
98            process.cmd = [wrkld] + pargs[idx].split()
99        else:
100            process.cmd = [wrkld]
101
102        if len(inputs) > idx:
103            process.input = inputs[idx]
104        if len(outputs) > idx:
105            process.output = outputs[idx]
106        if len(errouts) > idx:
107            process.errout = errouts[idx]
108
109        multiprocesses.append(process)
110        idx += 1
111
112    if options.smt:
113        assert(options.cpu_type == "detailed")
114        return multiprocesses, idx
115    else:
116        return multiprocesses, 1
117
118
119parser = optparse.OptionParser()
120Options.addCommonOptions(parser)
121Options.addSEOptions(parser)
122
123if '--ruby' in sys.argv:
124    Ruby.define_options(parser)
125
126(options, args) = parser.parse_args()
127
128if args:
129    print "Error: script doesn't take any positional arguments"
130    sys.exit(1)
131
132multiprocesses = []
133numThreads = 1
134
135if options.bench:
136    apps = options.bench.split("-")
137    if len(apps) != options.num_cpus:
138        print "number of benchmarks not equal to set num_cpus!"
139        sys.exit(1)
140
141    for app in apps:
142        try:
143            if buildEnv['TARGET_ISA'] == 'alpha':
144                exec("workload = %s('alpha', 'tru64', '%s')" % (
145                        app, options.spec_input))
146            elif buildEnv['TARGET_ISA'] == 'arm':
147                exec("workload = %s('arm_%s', 'linux', '%s')" % (
148                        app, options.arm_iset, options.spec_input))
149            else:
150                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
151                        app, options.spec_input))
152            multiprocesses.append(workload.makeLiveProcess())
153        except:
154            print >>sys.stderr, "Unable to find workload for %s: %s" % (
155                    buildEnv['TARGET_ISA'], app)
156            sys.exit(1)
157elif options.cmd:
158    multiprocesses, numThreads = get_processes(options)
159else:
160    print >> sys.stderr, "No workload specified. Exiting!\n"
161    sys.exit(1)
162
163
164(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
165CPUClass.numThreads = numThreads
166
167# Check -- do not allow SMT with multiple CPUs
168if options.smt and options.num_cpus > 1:
169    fatal("You cannot use SMT with multiple CPUs!")
170
171np = options.num_cpus
172system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
173                mem_mode = test_mem_mode,
174                mem_ranges = [AddrRange(options.mem_size)],
175                cache_line_size = options.cacheline_size)
176
177# Create a top-level voltage domain
178system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
179
180# Create a source clock for the system and set the clock period
181system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
182                                   voltage_domain = system.voltage_domain)
183
184# Create a CPU voltage domain
185system.cpu_voltage_domain = VoltageDomain()
186
187# Create a separate clock domain for the CPUs
188system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
189                                       voltage_domain =
190                                       system.cpu_voltage_domain)
191
192# All cpus belong to a common cpu_clk_domain, therefore running at a common
193# frequency.
194for cpu in system.cpu:
195    cpu.clk_domain = system.cpu_clk_domain
196
197if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
198    if buildEnv['TARGET_ISA'] == 'x86':
199        system.vm = KvmVM()
200        for process in multiprocesses:
201            process.useArchPT = True
202            process.kvmInSE = True
203    else:
204        fatal("KvmCPU can only be used in SE mode with x86")
205
206# Sanity check
207if options.fastmem:
208    if CPUClass != AtomicSimpleCPU:
209        fatal("Fastmem can only be used with atomic CPU!")
210    if (options.caches or options.l2cache):
211        fatal("You cannot use fastmem in combination with caches!")
212
213if options.simpoint_profile:
214    if not options.fastmem:
215        # Atomic CPU checked with fastmem option already
216        fatal("SimPoint generation should be done with atomic cpu and fastmem")
217    if np > 1:
218        fatal("SimPoint generation not supported with more than one CPUs")
219
220for i in xrange(np):
221    if options.smt:
222        system.cpu[i].workload = multiprocesses
223    elif len(multiprocesses) == 1:
224        system.cpu[i].workload = multiprocesses[0]
225    else:
226        system.cpu[i].workload = multiprocesses[i]
227
228    if options.fastmem:
229        system.cpu[i].fastmem = True
230
231    if options.simpoint_profile:
232        system.cpu[i].addSimPointProbe(options.simpoint_interval)
233
234    if options.checker:
235        system.cpu[i].addCheckerCpu()
236
237    system.cpu[i].createThreads()
238
239if options.ruby:
240    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
241        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
242        sys.exit(1)
243
244    Ruby.create_system(options, False, system)
245    assert(options.num_cpus == len(system.ruby._cpu_ports))
246
247    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
248                                        voltage_domain = system.voltage_domain)
249    for i in xrange(np):
250        ruby_port = system.ruby._cpu_ports[i]
251
252        # Create the interrupt controller and connect its ports to Ruby
253        # Note that the interrupt controller is always present but only
254        # in x86 does it have message ports that need to be connected
255        system.cpu[i].createInterruptController()
256
257        # Connect the cpu's cache ports to Ruby
258        system.cpu[i].icache_port = ruby_port.slave
259        system.cpu[i].dcache_port = ruby_port.slave
260        if buildEnv['TARGET_ISA'] == 'x86':
261            system.cpu[i].interrupts.pio = ruby_port.master
262            system.cpu[i].interrupts.int_master = ruby_port.slave
263            system.cpu[i].interrupts.int_slave = ruby_port.master
264            system.cpu[i].itb.walker.port = ruby_port.slave
265            system.cpu[i].dtb.walker.port = ruby_port.slave
266else:
267    MemClass = Simulation.setMemClass(options)
268    system.membus = SystemXBar()
269    system.system_port = system.membus.slave
270    CacheConfig.config_cache(options, system)
271    MemConfig.config_mem(options, system)
272
273root = Root(full_system = False, system = system)
274Simulation.run(options, root, system, FutureClass)
275