se.py revision 9800
14298Sgblack@eecs.umich.edu# Copyright (c) 2012-2013 ARM Limited 24298Sgblack@eecs.umich.edu# All rights reserved. 34298Sgblack@eecs.umich.edu# 44298Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 54298Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 64298Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 74298Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 84298Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 94298Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 104298Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 114298Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 124298Sgblack@eecs.umich.edu# 134298Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 144298Sgblack@eecs.umich.edu# All rights reserved. 154298Sgblack@eecs.umich.edu# 164298Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 174298Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 184298Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 194298Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 204298Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 214298Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 224298Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 234298Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 244298Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 254298Sgblack@eecs.umich.edu# this software without specific prior written permission. 264298Sgblack@eecs.umich.edu# 274298Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284298Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294298Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304298Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314298Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324298Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334298Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344298Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354298Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364298Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374298Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384298Sgblack@eecs.umich.edu# 394298Sgblack@eecs.umich.edu# Authors: Steve Reinhardt 404298Sgblack@eecs.umich.edu 414298Sgblack@eecs.umich.edu# Simple test script 424298Sgblack@eecs.umich.edu# 434298Sgblack@eecs.umich.edu# "m5 test.py" 444298Sgblack@eecs.umich.edu 454298Sgblack@eecs.umich.eduimport optparse 464298Sgblack@eecs.umich.eduimport sys 474298Sgblack@eecs.umich.edu 484298Sgblack@eecs.umich.eduimport m5 494298Sgblack@eecs.umich.edufrom m5.defines import buildEnv 504298Sgblack@eecs.umich.edufrom m5.objects import * 514298Sgblack@eecs.umich.edufrom m5.util import addToPath, fatal 524298Sgblack@eecs.umich.edu 534298Sgblack@eecs.umich.eduaddToPath('../common') 544298Sgblack@eecs.umich.eduaddToPath('../ruby') 554298Sgblack@eecs.umich.eduaddToPath('../topologies') 564338Sgblack@eecs.umich.edu 574338Sgblack@eecs.umich.eduimport Options 584338Sgblack@eecs.umich.eduimport Ruby 594524Sgblack@eecs.umich.eduimport Simulation 604524Sgblack@eecs.umich.eduimport CacheConfig 614524Sgblack@eecs.umich.edufrom Caches import * 624524Sgblack@eecs.umich.edufrom cpu2000 import * 634524Sgblack@eecs.umich.edu 644524Sgblack@eecs.umich.edudef get_processes(options): 654519Sgblack@eecs.umich.edu """Interprets provided options and returns a list of processes""" 664519Sgblack@eecs.umich.edu 67 multiprocesses = [] 68 inputs = [] 69 outputs = [] 70 errouts = [] 71 pargs = [] 72 73 workloads = options.cmd.split(';') 74 if options.input != "": 75 inputs = options.input.split(';') 76 if options.output != "": 77 outputs = options.output.split(';') 78 if options.errout != "": 79 errouts = options.errout.split(';') 80 if options.options != "": 81 pargs = options.options.split(';') 82 83 idx = 0 84 for wrkld in workloads: 85 process = LiveProcess() 86 process.executable = wrkld 87 88 if len(pargs) > idx: 89 process.cmd = [wrkld] + pargs[idx].split() 90 else: 91 process.cmd = [wrkld] 92 93 if len(inputs) > idx: 94 process.input = inputs[idx] 95 if len(outputs) > idx: 96 process.output = outputs[idx] 97 if len(errouts) > idx: 98 process.errout = errouts[idx] 99 100 multiprocesses.append(process) 101 idx += 1 102 103 if options.smt: 104 assert(options.cpu_type == "detailed" or options.cpu_type == "inorder") 105 return multiprocesses, idx 106 else: 107 return multiprocesses, 1 108 109 110parser = optparse.OptionParser() 111Options.addCommonOptions(parser) 112Options.addSEOptions(parser) 113 114if '--ruby' in sys.argv: 115 Ruby.define_options(parser) 116 117(options, args) = parser.parse_args() 118 119if args: 120 print "Error: script doesn't take any positional arguments" 121 sys.exit(1) 122 123multiprocesses = [] 124numThreads = 1 125 126if options.bench: 127 apps = options.bench.split("-") 128 if len(apps) != options.num_cpus: 129 print "number of benchmarks not equal to set num_cpus!" 130 sys.exit(1) 131 132 for app in apps: 133 try: 134 if buildEnv['TARGET_ISA'] == 'alpha': 135 exec("workload = %s('alpha', 'tru64', 'ref')" % app) 136 else: 137 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app) 138 multiprocesses.append(workload.makeLiveProcess()) 139 except: 140 print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) 141 sys.exit(1) 142elif options.cmd: 143 multiprocesses, numThreads = get_processes(options) 144else: 145 print >> sys.stderr, "No workload specified. Exiting!\n" 146 sys.exit(1) 147 148 149(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 150CPUClass.numThreads = numThreads 151 152MemClass = Simulation.setMemClass(options) 153 154# Check -- do not allow SMT with multiple CPUs 155if options.smt and options.num_cpus > 1: 156 fatal("You cannot use SMT with multiple CPUs!") 157 158np = options.num_cpus 159system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 160 physmem = MemClass(range=AddrRange(options.mem_size)), 161 mem_mode = test_mem_mode, 162 clk_domain = SrcClockDomain(clock = options.sys_clock)) 163 164# Create a separate clock domain for the CPUs 165system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock) 166 167# All cpus belong to a common cpu_clk_domain, therefore running at a common 168# frequency. 169for cpu in system.cpu: 170 cpu.clk_domain = system.cpu_clk_domain 171 172# Sanity check 173if options.fastmem: 174 if CPUClass != AtomicSimpleCPU: 175 fatal("Fastmem can only be used with atomic CPU!") 176 if (options.caches or options.l2cache): 177 fatal("You cannot use fastmem in combination with caches!") 178 179if options.simpoint_profile: 180 if not options.fastmem: 181 # Atomic CPU checked with fastmem option already 182 fatal("SimPoint generation should be done with atomic cpu and fastmem") 183 if np > 1: 184 fatal("SimPoint generation not supported with more than one CPUs") 185 186for i in xrange(np): 187 if options.smt: 188 system.cpu[i].workload = multiprocesses 189 elif len(multiprocesses) == 1: 190 system.cpu[i].workload = multiprocesses[0] 191 else: 192 system.cpu[i].workload = multiprocesses[i] 193 194 if options.fastmem: 195 system.cpu[i].fastmem = True 196 197 if options.simpoint_profile: 198 system.cpu[i].simpoint_profile = True 199 system.cpu[i].simpoint_interval = options.simpoint_interval 200 201 if options.checker: 202 system.cpu[i].addCheckerCpu() 203 204 system.cpu[i].createThreads() 205 206if options.ruby: 207 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 208 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 209 sys.exit(1) 210 211 # Set the option for physmem so that it is not allocated any space 212 system.physmem.null = True 213 214 options.use_map = True 215 Ruby.create_system(options, system) 216 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 217 218 for i in xrange(np): 219 ruby_port = system.ruby._cpu_ruby_ports[i] 220 221 # Create the interrupt controller and connect its ports to Ruby 222 # Note that the interrupt controller is always present but only 223 # in x86 does it have message ports that need to be connected 224 system.cpu[i].createInterruptController() 225 226 # Connect the cpu's cache ports to Ruby 227 system.cpu[i].icache_port = ruby_port.slave 228 system.cpu[i].dcache_port = ruby_port.slave 229 if buildEnv['TARGET_ISA'] == 'x86': 230 system.cpu[i].interrupts.pio = ruby_port.master 231 system.cpu[i].interrupts.int_master = ruby_port.slave 232 system.cpu[i].interrupts.int_slave = ruby_port.master 233 system.cpu[i].itb.walker.port = ruby_port.slave 234 system.cpu[i].dtb.walker.port = ruby_port.slave 235else: 236 system.membus = CoherentBus() 237 system.system_port = system.membus.slave 238 system.physmem.port = system.membus.master 239 CacheConfig.config_cache(options, system) 240 241root = Root(full_system = False, system = system) 242Simulation.run(options, root, system, FutureClass) 243