se.py revision 9100
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt 403005Sstever@eecs.umich.edu 412710SN/A# Simple test script 422710SN/A# 433005Sstever@eecs.umich.edu# "m5 test.py" 442889SN/A 456654Snate@binkert.orgimport optparse 466654Snate@binkert.orgimport sys 476654Snate@binkert.org 482667SN/Aimport m5 496654Snate@binkert.orgfrom m5.defines import buildEnv 506654Snate@binkert.orgfrom m5.objects import * 516654Snate@binkert.orgfrom m5.util import addToPath, fatal 525457Ssaidi@eecs.umich.edu 536654Snate@binkert.orgaddToPath('../common') 548169SLisa.Hsu@amd.comaddToPath('../ruby') 559100SBrad.Beckmann@amd.comaddToPath('../topologies') 568169SLisa.Hsu@amd.com 578920Snilay@cs.wisc.eduimport Options 588169SLisa.Hsu@amd.comimport Ruby 593395Shsul@eecs.umich.eduimport Simulation 606981SLisa.Hsu@amd.comimport CacheConfig 613448Shsul@eecs.umich.edufrom Caches import * 625369Ssaidi@eecs.umich.edufrom cpu2000 import * 633394Shsul@eecs.umich.edu 642957SN/Aparser = optparse.OptionParser() 658920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 668920Snilay@cs.wisc.eduOptions.addSEOptions(parser) 672957SN/A 688862Snilay@cs.wisc.eduif '--ruby' in sys.argv: 698862Snilay@cs.wisc.edu Ruby.define_options(parser) 708467Snilay@cs.wisc.edu 712957SN/A(options, args) = parser.parse_args() 722957SN/A 732957SN/Aif args: 742957SN/A print "Error: script doesn't take any positional arguments" 752957SN/A sys.exit(1) 762957SN/A 778167SLisa.Hsu@amd.commultiprocesses = [] 788167SLisa.Hsu@amd.comapps = [] 798167SLisa.Hsu@amd.com 805369Ssaidi@eecs.umich.eduif options.bench: 818167SLisa.Hsu@amd.com apps = options.bench.split("-") 828167SLisa.Hsu@amd.com if len(apps) != options.num_cpus: 838167SLisa.Hsu@amd.com print "number of benchmarks not equal to set num_cpus!" 848167SLisa.Hsu@amd.com sys.exit(1) 858167SLisa.Hsu@amd.com 868167SLisa.Hsu@amd.com for app in apps: 878167SLisa.Hsu@amd.com try: 888168SLisa.Hsu@amd.com if buildEnv['TARGET_ISA'] == 'alpha': 898168SLisa.Hsu@amd.com exec("workload = %s('alpha', 'tru64', 'ref')" % app) 908168SLisa.Hsu@amd.com else: 918168SLisa.Hsu@amd.com exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app) 928167SLisa.Hsu@amd.com multiprocesses.append(workload.makeLiveProcess()) 938167SLisa.Hsu@amd.com except: 948168SLisa.Hsu@amd.com print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) 955369Ssaidi@eecs.umich.edu sys.exit(1) 968920Snilay@cs.wisc.eduelif options.cmd: 975369Ssaidi@eecs.umich.edu process = LiveProcess() 985369Ssaidi@eecs.umich.edu process.executable = options.cmd 995369Ssaidi@eecs.umich.edu process.cmd = [options.cmd] + options.options.split() 1008167SLisa.Hsu@amd.com multiprocesses.append(process) 1018920Snilay@cs.wisc.eduelse: 1028920Snilay@cs.wisc.edu print >> sys.stderr, "No workload specified. Exiting!\n" 1038920Snilay@cs.wisc.edu sys.exit(1) 1045369Ssaidi@eecs.umich.edu 1055369Ssaidi@eecs.umich.edu 1062801SN/Aif options.input != "": 1072801SN/A process.input = options.input 1085514SMichael.Adler@intel.comif options.output != "": 1095514SMichael.Adler@intel.com process.output = options.output 1105514SMichael.Adler@intel.comif options.errout != "": 1115514SMichael.Adler@intel.com process.errout = options.errout 1122418SN/A 1136391Sksewell@umich.edu 1146391Sksewell@umich.edu# By default, set workload to path of user-specified binary 1156391Sksewell@umich.eduworkloads = options.cmd 1166642Sksewell@umich.edunumThreads = 1 1176391Sksewell@umich.edu 1188649Snilay@cs.wisc.eduif options.cpu_type == "detailed" or options.cpu_type == "inorder": 1192833SN/A #check for SMT workload 1202833SN/A workloads = options.cmd.split(';') 1212833SN/A if len(workloads) > 1: 1222833SN/A process = [] 1232833SN/A smt_idx = 0 1242833SN/A inputs = [] 1255514SMichael.Adler@intel.com outputs = [] 1265514SMichael.Adler@intel.com errouts = [] 1272833SN/A 1282833SN/A if options.input != "": 1292833SN/A inputs = options.input.split(';') 1305514SMichael.Adler@intel.com if options.output != "": 1315514SMichael.Adler@intel.com outputs = options.output.split(';') 1325514SMichael.Adler@intel.com if options.errout != "": 1335514SMichael.Adler@intel.com errouts = options.errout.split(';') 1342833SN/A 1352833SN/A for wrkld in workloads: 1362833SN/A smt_process = LiveProcess() 1373005Sstever@eecs.umich.edu smt_process.executable = wrkld 1382833SN/A smt_process.cmd = wrkld + " " + options.options 1392833SN/A if inputs and inputs[smt_idx]: 1402833SN/A smt_process.input = inputs[smt_idx] 1415514SMichael.Adler@intel.com if outputs and outputs[smt_idx]: 1425514SMichael.Adler@intel.com smt_process.output = outputs[smt_idx] 1435514SMichael.Adler@intel.com if errouts and errouts[smt_idx]: 1445514SMichael.Adler@intel.com smt_process.errout = errouts[smt_idx] 1452833SN/A process += [smt_process, ] 1462833SN/A smt_idx += 1 1476642Sksewell@umich.edu numThreads = len(workloads) 1488718Snilay@cs.wisc.edu 1498718Snilay@cs.wisc.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1503395Shsul@eecs.umich.eduCPUClass.clock = '2GHz' 1516642Sksewell@umich.eduCPUClass.numThreads = numThreads; 1523005Sstever@eecs.umich.edu 1533395Shsul@eecs.umich.edunp = options.num_cpus 1543395Shsul@eecs.umich.edu 1553395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1568931Sandreas.hansson@arm.com physmem = SimpleMemory(range=AddrRange("512MB")), 1579036Sandreas.hansson@arm.com membus = CoherentBus(), mem_mode = test_mem_mode) 1583395Shsul@eecs.umich.edu 1598926Sandreas.hansson@arm.com# Sanity check 1608926Sandreas.hansson@arm.comif options.fastmem and (options.caches or options.l2cache): 1618926Sandreas.hansson@arm.com fatal("You cannot use fastmem in combination with caches!") 1628926Sandreas.hansson@arm.com 1633395Shsul@eecs.umich.edufor i in xrange(np): 1648957Sjayneel@cs.wisc.edu if len(multiprocesses) == 1: 1658957Sjayneel@cs.wisc.edu system.cpu[i].workload = multiprocesses[0] 1668957Sjayneel@cs.wisc.edu else: 1678957Sjayneel@cs.wisc.edu system.cpu[i].workload = multiprocesses[i] 1683005Sstever@eecs.umich.edu 1694968Sacolyte@umich.edu if options.fastmem: 1709006Sandreas.hansson@arm.com system.cpu[i].fastmem = True 1714968Sacolyte@umich.edu 1728887Sgeoffrey.blake@arm.com if options.checker: 1738887Sgeoffrey.blake@arm.com system.cpu[i].addCheckerCpu() 1748887Sgeoffrey.blake@arm.com 1758887Sgeoffrey.blake@arm.comif options.ruby: 1768896Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 1778896Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 1788896Snilay@cs.wisc.edu sys.exit(1) 1798896Snilay@cs.wisc.edu 1808887Sgeoffrey.blake@arm.com options.use_map = True 1818887Sgeoffrey.blake@arm.com Ruby.create_system(options, system) 1828887Sgeoffrey.blake@arm.com assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 1838896Snilay@cs.wisc.edu 1848896Snilay@cs.wisc.edu for i in xrange(np): 1858896Snilay@cs.wisc.edu ruby_port = system.ruby._cpu_ruby_ports[i] 1868896Snilay@cs.wisc.edu 1878896Snilay@cs.wisc.edu # Create the interrupt controller and connect its ports to Ruby 1888896Snilay@cs.wisc.edu system.cpu[i].createInterruptController() 1898896Snilay@cs.wisc.edu system.cpu[i].interrupts.pio = ruby_port.master 1908896Snilay@cs.wisc.edu system.cpu[i].interrupts.int_master = ruby_port.slave 1918896Snilay@cs.wisc.edu system.cpu[i].interrupts.int_slave = ruby_port.master 1928896Snilay@cs.wisc.edu 1938896Snilay@cs.wisc.edu # Connect the cpu's cache ports to Ruby 1948896Snilay@cs.wisc.edu system.cpu[i].icache_port = ruby_port.slave 1958896Snilay@cs.wisc.edu system.cpu[i].dcache_port = ruby_port.slave 1968887Sgeoffrey.blake@arm.comelse: 1978887Sgeoffrey.blake@arm.com system.system_port = system.membus.slave 1988887Sgeoffrey.blake@arm.com system.physmem.port = system.membus.master 1998887Sgeoffrey.blake@arm.com CacheConfig.config_cache(options, system) 2008887Sgeoffrey.blake@arm.com 2018801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 2023481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass) 203