se.py revision 6642
15369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 23005Sstever@eecs.umich.edu# All rights reserved. 33005Sstever@eecs.umich.edu# 43005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 63005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133005Sstever@eecs.umich.edu# this software without specific prior written permission. 143005Sstever@eecs.umich.edu# 153005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# Authors: Steve Reinhardt 283005Sstever@eecs.umich.edu 292710SN/A# Simple test script 302710SN/A# 313005Sstever@eecs.umich.edu# "m5 test.py" 322889SN/A 332667SN/Aimport m5 345457Ssaidi@eecs.umich.edu 355457Ssaidi@eecs.umich.eduif m5.build_env['FULL_SYSTEM']: 365822Ssaidi@eecs.umich.edu m5.fatal("This script requires syscall emulation mode (*_SE).") 375457Ssaidi@eecs.umich.edu 383005Sstever@eecs.umich.edufrom m5.objects import * 392856SN/Aimport os, optparse, sys 405514SMichael.Adler@intel.comfrom os.path import join as joinpath 412917SN/Am5.AddToPath('../common') 423395Shsul@eecs.umich.eduimport Simulation 433448Shsul@eecs.umich.edufrom Caches import * 445369Ssaidi@eecs.umich.edufrom cpu2000 import * 453394Shsul@eecs.umich.edu 463444Sktlim@umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 473444Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 483444Sktlim@umich.educonfig_root = os.path.dirname(config_path) 493444Sktlim@umich.edum5_root = os.path.dirname(config_root) 502424SN/A 512957SN/Aparser = optparse.OptionParser() 522957SN/A 533323Shsul@eecs.umich.edu# Benchmark options 543005Sstever@eecs.umich.eduparser.add_option("-c", "--cmd", 555514SMichael.Adler@intel.com default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"), 565514SMichael.Adler@intel.com help="The binary to run in syscall emulation mode.") 572957SN/Aparser.add_option("-o", "--options", default="", 585514SMichael.Adler@intel.com help='The options to pass to the binary, use " " around the entire string') 595514SMichael.Adler@intel.comparser.add_option("-i", "--input", default="", help="Read stdin from a file.") 605514SMichael.Adler@intel.comparser.add_option("--output", default="", help="Redirect stdout to a file.") 615514SMichael.Adler@intel.comparser.add_option("--errout", default="", help="Redirect stderr to a file.") 623323Shsul@eecs.umich.edu 633444Sktlim@umich.eduexecfile(os.path.join(config_root, "common", "Options.py")) 642957SN/A 652957SN/A(options, args) = parser.parse_args() 662957SN/A 672957SN/Aif args: 682957SN/A print "Error: script doesn't take any positional arguments" 692957SN/A sys.exit(1) 702957SN/A 715369Ssaidi@eecs.umich.eduif options.bench: 725369Ssaidi@eecs.umich.edu try: 735369Ssaidi@eecs.umich.edu if m5.build_env['TARGET_ISA'] != 'alpha': 745369Ssaidi@eecs.umich.edu print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time" 755369Ssaidi@eecs.umich.edu sys.exit(1) 765369Ssaidi@eecs.umich.edu exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench) 775369Ssaidi@eecs.umich.edu process = workload.makeLiveProcess() 785369Ssaidi@eecs.umich.edu except: 795369Ssaidi@eecs.umich.edu print >>sys.stderr, "Unable to find workload for %s" % options.bench 805369Ssaidi@eecs.umich.edu sys.exit(1) 815369Ssaidi@eecs.umich.eduelse: 825369Ssaidi@eecs.umich.edu process = LiveProcess() 835369Ssaidi@eecs.umich.edu process.executable = options.cmd 845369Ssaidi@eecs.umich.edu process.cmd = [options.cmd] + options.options.split() 855369Ssaidi@eecs.umich.edu 865369Ssaidi@eecs.umich.edu 872801SN/Aif options.input != "": 882801SN/A process.input = options.input 895514SMichael.Adler@intel.comif options.output != "": 905514SMichael.Adler@intel.com process.output = options.output 915514SMichael.Adler@intel.comif options.errout != "": 925514SMichael.Adler@intel.com process.errout = options.errout 932418SN/A 946391Sksewell@umich.edu 956391Sksewell@umich.edu# By default, set workload to path of user-specified binary 966391Sksewell@umich.eduworkloads = options.cmd 976642Sksewell@umich.edunumThreads = 1 986391Sksewell@umich.edu 996642Sksewell@umich.eduif options.detailed or options.inorder: 1002833SN/A #check for SMT workload 1012833SN/A workloads = options.cmd.split(';') 1022833SN/A if len(workloads) > 1: 1032833SN/A process = [] 1042833SN/A smt_idx = 0 1052833SN/A inputs = [] 1065514SMichael.Adler@intel.com outputs = [] 1075514SMichael.Adler@intel.com errouts = [] 1082833SN/A 1092833SN/A if options.input != "": 1102833SN/A inputs = options.input.split(';') 1115514SMichael.Adler@intel.com if options.output != "": 1125514SMichael.Adler@intel.com outputs = options.output.split(';') 1135514SMichael.Adler@intel.com if options.errout != "": 1145514SMichael.Adler@intel.com errouts = options.errout.split(';') 1152833SN/A 1162833SN/A for wrkld in workloads: 1172833SN/A smt_process = LiveProcess() 1183005Sstever@eecs.umich.edu smt_process.executable = wrkld 1192833SN/A smt_process.cmd = wrkld + " " + options.options 1202833SN/A if inputs and inputs[smt_idx]: 1212833SN/A smt_process.input = inputs[smt_idx] 1225514SMichael.Adler@intel.com if outputs and outputs[smt_idx]: 1235514SMichael.Adler@intel.com smt_process.output = outputs[smt_idx] 1245514SMichael.Adler@intel.com if errouts and errouts[smt_idx]: 1255514SMichael.Adler@intel.com smt_process.errout = errouts[smt_idx] 1262833SN/A process += [smt_process, ] 1272833SN/A smt_idx += 1 1286642Sksewell@umich.edu numThreads = len(workloads) 1296642Sksewell@umich.edu 1303481Shsul@eecs.umich.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1312957SN/A 1323395Shsul@eecs.umich.eduCPUClass.clock = '2GHz' 1336642Sksewell@umich.eduCPUClass.numThreads = numThreads; 1343005Sstever@eecs.umich.edu 1353395Shsul@eecs.umich.edunp = options.num_cpus 1363395Shsul@eecs.umich.edu 1373395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1383323Shsul@eecs.umich.edu physmem = PhysicalMemory(range=AddrRange("512MB")), 1393395Shsul@eecs.umich.edu membus = Bus(), mem_mode = test_mem_mode) 1403395Shsul@eecs.umich.edu 1413005Sstever@eecs.umich.edusystem.physmem.port = system.membus.port 1423395Shsul@eecs.umich.edu 1435056Ssaidi@eecs.umich.eduif options.l2cache: 1445056Ssaidi@eecs.umich.edu system.l2 = L2Cache(size='2MB') 1455056Ssaidi@eecs.umich.edu system.tol2bus = Bus() 1465056Ssaidi@eecs.umich.edu system.l2.cpu_side = system.tol2bus.port 1475056Ssaidi@eecs.umich.edu system.l2.mem_side = system.membus.port 1485056Ssaidi@eecs.umich.edu 1493395Shsul@eecs.umich.edufor i in xrange(np): 1503514Sktlim@umich.edu if options.caches: 1513395Shsul@eecs.umich.edu system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 1523448Shsul@eecs.umich.edu L1Cache(size = '64kB')) 1534455Ssaidi@eecs.umich.edu if options.l2cache: 1544455Ssaidi@eecs.umich.edu system.cpu[i].connectMemPorts(system.tol2bus) 1554455Ssaidi@eecs.umich.edu else: 1564455Ssaidi@eecs.umich.edu system.cpu[i].connectMemPorts(system.membus) 1573395Shsul@eecs.umich.edu system.cpu[i].workload = process 1583005Sstever@eecs.umich.edu 1594968Sacolyte@umich.edu if options.fastmem: 1604968Sacolyte@umich.edu system.cpu[0].physmem_port = system.physmem.port 1614968Sacolyte@umich.edu 1623005Sstever@eecs.umich.eduroot = Root(system = system) 1632902SN/A 1643481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass) 165