se.py revision 12941
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt 403005Sstever@eecs.umich.edu 412710SN/A# Simple test script 422710SN/A# 433005Sstever@eecs.umich.edu# "m5 test.py" 442889SN/A 4512564Sgabeblack@google.comfrom __future__ import print_function 4612564Sgabeblack@google.com 476654Snate@binkert.orgimport optparse 486654Snate@binkert.orgimport sys 499907Snilay@cs.wisc.eduimport os 506654Snate@binkert.org 512667SN/Aimport m5 526654Snate@binkert.orgfrom m5.defines import buildEnv 536654Snate@binkert.orgfrom m5.objects import * 5412395Sswapnilster@gmail.comfrom m5.util import addToPath, fatal, warn 555457Ssaidi@eecs.umich.edu 5611670Sandreas.hansson@arm.comaddToPath('../') 5711670Sandreas.hansson@arm.com 5811670Sandreas.hansson@arm.comfrom ruby import Ruby 598169SLisa.Hsu@amd.com 6011682Sandreas.hansson@arm.comfrom common import Options 6111682Sandreas.hansson@arm.comfrom common import Simulation 6211682Sandreas.hansson@arm.comfrom common import CacheConfig 6311682Sandreas.hansson@arm.comfrom common import CpuConfig 6411682Sandreas.hansson@arm.comfrom common import MemConfig 6511682Sandreas.hansson@arm.comfrom common.Caches import * 6611682Sandreas.hansson@arm.comfrom common.cpu2000 import * 673394Shsul@eecs.umich.edu 689197Snilay@cs.wisc.edudef get_processes(options): 699197Snilay@cs.wisc.edu """Interprets provided options and returns a list of processes""" 709197Snilay@cs.wisc.edu 719197Snilay@cs.wisc.edu multiprocesses = [] 729197Snilay@cs.wisc.edu inputs = [] 739197Snilay@cs.wisc.edu outputs = [] 749197Snilay@cs.wisc.edu errouts = [] 759197Snilay@cs.wisc.edu pargs = [] 769197Snilay@cs.wisc.edu 779197Snilay@cs.wisc.edu workloads = options.cmd.split(';') 789197Snilay@cs.wisc.edu if options.input != "": 799197Snilay@cs.wisc.edu inputs = options.input.split(';') 809197Snilay@cs.wisc.edu if options.output != "": 819197Snilay@cs.wisc.edu outputs = options.output.split(';') 829197Snilay@cs.wisc.edu if options.errout != "": 839197Snilay@cs.wisc.edu errouts = options.errout.split(';') 849197Snilay@cs.wisc.edu if options.options != "": 859197Snilay@cs.wisc.edu pargs = options.options.split(';') 869197Snilay@cs.wisc.edu 879197Snilay@cs.wisc.edu idx = 0 889197Snilay@cs.wisc.edu for wrkld in workloads: 8912146Spau.cabre@metempsy.com process = Process(pid = 100 + idx) 909197Snilay@cs.wisc.edu process.executable = wrkld 919907Snilay@cs.wisc.edu process.cwd = os.getcwd() 929197Snilay@cs.wisc.edu 9310803Sbrandon.potter@amd.com if options.env: 9410803Sbrandon.potter@amd.com with open(options.env, 'r') as f: 9510803Sbrandon.potter@amd.com process.env = [line.rstrip() for line in f] 9610803Sbrandon.potter@amd.com 979197Snilay@cs.wisc.edu if len(pargs) > idx: 989217Snilay@cs.wisc.edu process.cmd = [wrkld] + pargs[idx].split() 999197Snilay@cs.wisc.edu else: 1009197Snilay@cs.wisc.edu process.cmd = [wrkld] 1019197Snilay@cs.wisc.edu 1029197Snilay@cs.wisc.edu if len(inputs) > idx: 1039197Snilay@cs.wisc.edu process.input = inputs[idx] 1049197Snilay@cs.wisc.edu if len(outputs) > idx: 1059197Snilay@cs.wisc.edu process.output = outputs[idx] 1069197Snilay@cs.wisc.edu if len(errouts) > idx: 1079197Snilay@cs.wisc.edu process.errout = errouts[idx] 1089197Snilay@cs.wisc.edu 1099197Snilay@cs.wisc.edu multiprocesses.append(process) 1109197Snilay@cs.wisc.edu idx += 1 1119197Snilay@cs.wisc.edu 1129197Snilay@cs.wisc.edu if options.smt: 11312014Sgabeblack@google.com assert(options.cpu_type == "DerivO3CPU") 1149197Snilay@cs.wisc.edu return multiprocesses, idx 1159197Snilay@cs.wisc.edu else: 1169197Snilay@cs.wisc.edu return multiprocesses, 1 1179197Snilay@cs.wisc.edu 1189197Snilay@cs.wisc.edu 1192957SN/Aparser = optparse.OptionParser() 1208920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 1218920Snilay@cs.wisc.eduOptions.addSEOptions(parser) 1222957SN/A 1238862Snilay@cs.wisc.eduif '--ruby' in sys.argv: 1248862Snilay@cs.wisc.edu Ruby.define_options(parser) 1258467Snilay@cs.wisc.edu 1262957SN/A(options, args) = parser.parse_args() 1272957SN/A 1282957SN/Aif args: 12912564Sgabeblack@google.com print("Error: script doesn't take any positional arguments") 1302957SN/A sys.exit(1) 1312957SN/A 1328167SLisa.Hsu@amd.commultiprocesses = [] 1339197Snilay@cs.wisc.edunumThreads = 1 1348167SLisa.Hsu@amd.com 1355369Ssaidi@eecs.umich.eduif options.bench: 1368167SLisa.Hsu@amd.com apps = options.bench.split("-") 1378167SLisa.Hsu@amd.com if len(apps) != options.num_cpus: 13812564Sgabeblack@google.com print("number of benchmarks not equal to set num_cpus!") 1398167SLisa.Hsu@amd.com sys.exit(1) 1408167SLisa.Hsu@amd.com 1418167SLisa.Hsu@amd.com for app in apps: 1428167SLisa.Hsu@amd.com try: 1438168SLisa.Hsu@amd.com if buildEnv['TARGET_ISA'] == 'alpha': 14410037SARM gem5 Developers exec("workload = %s('alpha', 'tru64', '%s')" % ( 14510037SARM gem5 Developers app, options.spec_input)) 14610037SARM gem5 Developers elif buildEnv['TARGET_ISA'] == 'arm': 14710037SARM gem5 Developers exec("workload = %s('arm_%s', 'linux', '%s')" % ( 14810037SARM gem5 Developers app, options.arm_iset, options.spec_input)) 1498168SLisa.Hsu@amd.com else: 15010037SARM gem5 Developers exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 15110037SARM gem5 Developers app, options.spec_input)) 15211851Sbrandon.potter@amd.com multiprocesses.append(workload.makeProcess()) 1538167SLisa.Hsu@amd.com except: 15412564Sgabeblack@google.com print("Unable to find workload for %s: %s" % 15512564Sgabeblack@google.com (buildEnv['TARGET_ISA'], app), 15612564Sgabeblack@google.com file=sys.stderr) 1575369Ssaidi@eecs.umich.edu sys.exit(1) 1588920Snilay@cs.wisc.eduelif options.cmd: 1599197Snilay@cs.wisc.edu multiprocesses, numThreads = get_processes(options) 1608920Snilay@cs.wisc.eduelse: 16112564Sgabeblack@google.com print("No workload specified. Exiting!\n", file=sys.stderr) 1628920Snilay@cs.wisc.edu sys.exit(1) 1635369Ssaidi@eecs.umich.edu 1645369Ssaidi@eecs.umich.edu 1658718Snilay@cs.wisc.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1669197Snilay@cs.wisc.eduCPUClass.numThreads = numThreads 1679197Snilay@cs.wisc.edu 1689197Snilay@cs.wisc.edu# Check -- do not allow SMT with multiple CPUs 1699197Snilay@cs.wisc.eduif options.smt and options.num_cpus > 1: 1709197Snilay@cs.wisc.edu fatal("You cannot use SMT with multiple CPUs!") 1713005Sstever@eecs.umich.edu 1723395Shsul@eecs.umich.edunp = options.num_cpus 1733395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1749793Sakash.bagdia@arm.com mem_mode = test_mem_mode, 1759836Sandreas.hansson@arm.com mem_ranges = [AddrRange(options.mem_size)], 1769815SAndreas Hansson <andreas.hansson> cache_line_size = options.cacheline_size) 1779793Sakash.bagdia@arm.com 17811147Smitch.hayenga@arm.comif numThreads > 1: 17911147Smitch.hayenga@arm.com system.multi_thread = True 18011147Smitch.hayenga@arm.com 1819827Sakash.bagdia@arm.com# Create a top-level voltage domain 1829827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1839827Sakash.bagdia@arm.com 1849827Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period 1859827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 1869827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 1879827Sakash.bagdia@arm.com 1889827Sakash.bagdia@arm.com# Create a CPU voltage domain 1899827Sakash.bagdia@arm.comsystem.cpu_voltage_domain = VoltageDomain() 1909827Sakash.bagdia@arm.com 1919793Sakash.bagdia@arm.com# Create a separate clock domain for the CPUs 1929827Sakash.bagdia@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1939827Sakash.bagdia@arm.com voltage_domain = 1949827Sakash.bagdia@arm.com system.cpu_voltage_domain) 1959793Sakash.bagdia@arm.com 19611251Sradhika.jagtap@ARM.com# If elastic tracing is enabled, then configure the cpu and attach the elastic 19711251Sradhika.jagtap@ARM.com# trace probe 19811251Sradhika.jagtap@ARM.comif options.elastic_trace_en: 19911251Sradhika.jagtap@ARM.com CpuConfig.config_etrace(CPUClass, system.cpu, options) 20011251Sradhika.jagtap@ARM.com 2019793Sakash.bagdia@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 2029793Sakash.bagdia@arm.com# frequency. 2039793Sakash.bagdia@arm.comfor cpu in system.cpu: 2049793Sakash.bagdia@arm.com cpu.clk_domain = system.cpu_clk_domain 2053395Shsul@eecs.umich.edu 20612941Sandreas.sandberg@arm.comif CpuConfig.is_kvm_cpu(CPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 20710555Salexandru.dutu@amd.com if buildEnv['TARGET_ISA'] == 'x86': 20811839SCurtis.Dunham@arm.com system.kvm_vm = KvmVM() 20910555Salexandru.dutu@amd.com for process in multiprocesses: 21010555Salexandru.dutu@amd.com process.useArchPT = True 21110555Salexandru.dutu@amd.com process.kvmInSE = True 21210555Salexandru.dutu@amd.com else: 21310555Salexandru.dutu@amd.com fatal("KvmCPU can only be used in SE mode with x86") 21410555Salexandru.dutu@amd.com 2158926Sandreas.hansson@arm.com# Sanity check 2169317Sandreas.hansson@arm.comif options.fastmem: 2179317Sandreas.hansson@arm.com if CPUClass != AtomicSimpleCPU: 2189317Sandreas.hansson@arm.com fatal("Fastmem can only be used with atomic CPU!") 2199317Sandreas.hansson@arm.com if (options.caches or options.l2cache): 2209317Sandreas.hansson@arm.com fatal("You cannot use fastmem in combination with caches!") 2218926Sandreas.hansson@arm.com 2229647Sdam.sunwoo@arm.comif options.simpoint_profile: 2239647Sdam.sunwoo@arm.com if not options.fastmem: 2249647Sdam.sunwoo@arm.com # Atomic CPU checked with fastmem option already 2259647Sdam.sunwoo@arm.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 2269647Sdam.sunwoo@arm.com if np > 1: 2279647Sdam.sunwoo@arm.com fatal("SimPoint generation not supported with more than one CPUs") 2289647Sdam.sunwoo@arm.com 2293395Shsul@eecs.umich.edufor i in xrange(np): 2309197Snilay@cs.wisc.edu if options.smt: 2319197Snilay@cs.wisc.edu system.cpu[i].workload = multiprocesses 2329197Snilay@cs.wisc.edu elif len(multiprocesses) == 1: 2338957Sjayneel@cs.wisc.edu system.cpu[i].workload = multiprocesses[0] 2348957Sjayneel@cs.wisc.edu else: 2358957Sjayneel@cs.wisc.edu system.cpu[i].workload = multiprocesses[i] 2363005Sstever@eecs.umich.edu 2374968Sacolyte@umich.edu if options.fastmem: 2389006Sandreas.hansson@arm.com system.cpu[i].fastmem = True 2394968Sacolyte@umich.edu 2409647Sdam.sunwoo@arm.com if options.simpoint_profile: 24110381Sdam.sunwoo@arm.com system.cpu[i].addSimPointProbe(options.simpoint_interval) 2429647Sdam.sunwoo@arm.com 2438887Sgeoffrey.blake@arm.com if options.checker: 2448887Sgeoffrey.blake@arm.com system.cpu[i].addCheckerCpu() 2458887Sgeoffrey.blake@arm.com 2469384SAndreas.Sandberg@arm.com system.cpu[i].createThreads() 2479384SAndreas.Sandberg@arm.com 2488887Sgeoffrey.blake@arm.comif options.ruby: 24910519Snilay@cs.wisc.edu Ruby.create_system(options, False, system) 25010120Snilay@cs.wisc.edu assert(options.num_cpus == len(system.ruby._cpu_ports)) 2518896Snilay@cs.wisc.edu 25210300Scastilloe@unican.es system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 25310300Scastilloe@unican.es voltage_domain = system.voltage_domain) 2548896Snilay@cs.wisc.edu for i in xrange(np): 25510120Snilay@cs.wisc.edu ruby_port = system.ruby._cpu_ports[i] 2568896Snilay@cs.wisc.edu 2578896Snilay@cs.wisc.edu # Create the interrupt controller and connect its ports to Ruby 2589268Smalek.musleh@gmail.com # Note that the interrupt controller is always present but only 2599268Smalek.musleh@gmail.com # in x86 does it have message ports that need to be connected 2608896Snilay@cs.wisc.edu system.cpu[i].createInterruptController() 2618896Snilay@cs.wisc.edu 2628896Snilay@cs.wisc.edu # Connect the cpu's cache ports to Ruby 2638896Snilay@cs.wisc.edu system.cpu[i].icache_port = ruby_port.slave 2648896Snilay@cs.wisc.edu system.cpu[i].dcache_port = ruby_port.slave 2659222Shestness@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'x86': 26611150Smitch.hayenga@arm.com system.cpu[i].interrupts[0].pio = ruby_port.master 26711150Smitch.hayenga@arm.com system.cpu[i].interrupts[0].int_master = ruby_port.slave 26811150Smitch.hayenga@arm.com system.cpu[i].interrupts[0].int_slave = ruby_port.master 2699222Shestness@cs.wisc.edu system.cpu[i].itb.walker.port = ruby_port.slave 2709222Shestness@cs.wisc.edu system.cpu[i].dtb.walker.port = ruby_port.slave 2718887Sgeoffrey.blake@arm.comelse: 27210150Snilay@cs.wisc.edu MemClass = Simulation.setMemClass(options) 27310720Sandreas.hansson@arm.com system.membus = SystemXBar() 2748887Sgeoffrey.blake@arm.com system.system_port = system.membus.slave 2758887Sgeoffrey.blake@arm.com CacheConfig.config_cache(options, system) 2769836Sandreas.hansson@arm.com MemConfig.config_mem(options, system) 2778887Sgeoffrey.blake@arm.com 2788801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 2793481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass) 280