se.py revision 10300
13569Sgblack@eecs.umich.edu# Copyright (c) 2012-2013 ARM Limited 23569Sgblack@eecs.umich.edu# All rights reserved. 33569Sgblack@eecs.umich.edu# 43569Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 53569Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 63569Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 73569Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 83569Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 93569Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 103569Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 113569Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 123569Sgblack@eecs.umich.edu# 133569Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 143569Sgblack@eecs.umich.edu# All rights reserved. 153569Sgblack@eecs.umich.edu# 163569Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173569Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 183569Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193569Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203569Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213569Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223569Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233569Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243569Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253569Sgblack@eecs.umich.edu# this software without specific prior written permission. 263569Sgblack@eecs.umich.edu# 273569Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283804Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293569Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303569Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3111793Sbrandon.potter@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3211793Sbrandon.potter@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333918Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343918Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353804Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 367678Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 376335Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383824Ssaidi@eecs.umich.edu# 393811Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 408229Snate@binkert.org 413811Ssaidi@eecs.umich.edu# Simple test script 428232Snate@binkert.org# 438232Snate@binkert.org# "m5 test.py" 443823Ssaidi@eecs.umich.edu 453823Ssaidi@eecs.umich.eduimport optparse 468751Sgblack@eecs.umich.eduimport sys 474103Ssaidi@eecs.umich.eduimport os 483569Sgblack@eecs.umich.edu 493804Ssaidi@eecs.umich.eduimport m5 503804Ssaidi@eecs.umich.edufrom m5.defines import buildEnv 514088Sbinkertn@umich.edufrom m5.objects import * 523569Sgblack@eecs.umich.edufrom m5.util import addToPath, fatal 535034Smilesck@eecs.umich.edu 545358Sgblack@eecs.umich.eduaddToPath('../common') 558374Sksewell@umich.eduaddToPath('../ruby') 563804Ssaidi@eecs.umich.edu 573804Ssaidi@eecs.umich.eduimport Options 583804Ssaidi@eecs.umich.eduimport Ruby 595555Snate@binkert.orgimport Simulation 603569Sgblack@eecs.umich.eduimport CacheConfig 613804Ssaidi@eecs.umich.eduimport MemConfig 623918Ssaidi@eecs.umich.edufrom Caches import * 633881Ssaidi@eecs.umich.edufrom cpu2000 import * 643881Ssaidi@eecs.umich.edu 653881Ssaidi@eecs.umich.edudef get_processes(options): 664990Sgblack@eecs.umich.edu """Interprets provided options and returns a list of processes""" 674990Sgblack@eecs.umich.edu 684990Sgblack@eecs.umich.edu multiprocesses = [] 694990Sgblack@eecs.umich.edu inputs = [] 704990Sgblack@eecs.umich.edu outputs = [] 714990Sgblack@eecs.umich.edu errouts = [] 724990Sgblack@eecs.umich.edu pargs = [] 734990Sgblack@eecs.umich.edu 744990Sgblack@eecs.umich.edu workloads = options.cmd.split(';') 756022Sgblack@eecs.umich.edu if options.input != "": 766022Sgblack@eecs.umich.edu inputs = options.input.split(';') 776022Sgblack@eecs.umich.edu if options.output != "": 783804Ssaidi@eecs.umich.edu outputs = options.output.split(';') 793569Sgblack@eecs.umich.edu if options.errout != "": 803804Ssaidi@eecs.umich.edu errouts = options.errout.split(';') 813804Ssaidi@eecs.umich.edu if options.options != "": 823804Ssaidi@eecs.umich.edu pargs = options.options.split(';') 833804Ssaidi@eecs.umich.edu 843881Ssaidi@eecs.umich.edu idx = 0 853804Ssaidi@eecs.umich.edu for wrkld in workloads: 863804Ssaidi@eecs.umich.edu process = LiveProcess() 873804Ssaidi@eecs.umich.edu process.executable = wrkld 883804Ssaidi@eecs.umich.edu process.cwd = os.getcwd() 893804Ssaidi@eecs.umich.edu 903804Ssaidi@eecs.umich.edu if len(pargs) > idx: 913804Ssaidi@eecs.umich.edu process.cmd = [wrkld] + pargs[idx].split() 923569Sgblack@eecs.umich.edu else: 933569Sgblack@eecs.umich.edu process.cmd = [wrkld] 943804Ssaidi@eecs.umich.edu 953804Ssaidi@eecs.umich.edu if len(inputs) > idx: 963826Ssaidi@eecs.umich.edu process.input = inputs[idx] 973804Ssaidi@eecs.umich.edu if len(outputs) > idx: 983804Ssaidi@eecs.umich.edu process.output = outputs[idx] 993826Ssaidi@eecs.umich.edu if len(errouts) > idx: 1003907Ssaidi@eecs.umich.edu process.errout = errouts[idx] 1013826Ssaidi@eecs.umich.edu 1023811Ssaidi@eecs.umich.edu multiprocesses.append(process) 1033836Ssaidi@eecs.umich.edu idx += 1 1043915Ssaidi@eecs.umich.edu 1053907Ssaidi@eecs.umich.edu if options.smt: 1063881Ssaidi@eecs.umich.edu assert(options.cpu_type == "detailed" or options.cpu_type == "inorder") 1073881Ssaidi@eecs.umich.edu return multiprocesses, idx 1083881Ssaidi@eecs.umich.edu else: 1093881Ssaidi@eecs.umich.edu return multiprocesses, 1 1103907Ssaidi@eecs.umich.edu 1113881Ssaidi@eecs.umich.edu 1125555Snate@binkert.orgparser = optparse.OptionParser() 1135555Snate@binkert.orgOptions.addCommonOptions(parser) 1145555Snate@binkert.orgOptions.addSEOptions(parser) 1153881Ssaidi@eecs.umich.edu 1163881Ssaidi@eecs.umich.eduif '--ruby' in sys.argv: 1173907Ssaidi@eecs.umich.edu Ruby.define_options(parser) 1183907Ssaidi@eecs.umich.edu 1193907Ssaidi@eecs.umich.edu(options, args) = parser.parse_args() 1203907Ssaidi@eecs.umich.edu 1213907Ssaidi@eecs.umich.eduif args: 1223907Ssaidi@eecs.umich.edu print "Error: script doesn't take any positional arguments" 1233907Ssaidi@eecs.umich.edu sys.exit(1) 1243907Ssaidi@eecs.umich.edu 1253907Ssaidi@eecs.umich.edumultiprocesses = [] 1263907Ssaidi@eecs.umich.edunumThreads = 1 1273907Ssaidi@eecs.umich.edu 1283907Ssaidi@eecs.umich.eduif options.bench: 1293907Ssaidi@eecs.umich.edu apps = options.bench.split("-") 1303907Ssaidi@eecs.umich.edu if len(apps) != options.num_cpus: 1313907Ssaidi@eecs.umich.edu print "number of benchmarks not equal to set num_cpus!" 1323907Ssaidi@eecs.umich.edu sys.exit(1) 1333907Ssaidi@eecs.umich.edu 1343907Ssaidi@eecs.umich.edu for app in apps: 1353907Ssaidi@eecs.umich.edu try: 1363907Ssaidi@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 1373907Ssaidi@eecs.umich.edu exec("workload = %s('alpha', 'tru64', '%s')" % ( 1383826Ssaidi@eecs.umich.edu app, options.spec_input)) 1393826Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1403826Ssaidi@eecs.umich.edu exec("workload = %s('arm_%s', 'linux', '%s')" % ( 1413826Ssaidi@eecs.umich.edu app, options.arm_iset, options.spec_input)) 1423881Ssaidi@eecs.umich.edu else: 1433881Ssaidi@eecs.umich.edu exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 1443881Ssaidi@eecs.umich.edu app, options.spec_input)) 1453881Ssaidi@eecs.umich.edu multiprocesses.append(workload.makeLiveProcess()) 1463881Ssaidi@eecs.umich.edu except: 1473881Ssaidi@eecs.umich.edu print >>sys.stderr, "Unable to find workload for %s: %s" % ( 1483881Ssaidi@eecs.umich.edu buildEnv['TARGET_ISA'], app) 1493881Ssaidi@eecs.umich.edu sys.exit(1) 1503881Ssaidi@eecs.umich.eduelif options.cmd: 1513881Ssaidi@eecs.umich.edu multiprocesses, numThreads = get_processes(options) 1523881Ssaidi@eecs.umich.eduelse: 1533881Ssaidi@eecs.umich.edu print >> sys.stderr, "No workload specified. Exiting!\n" 1543881Ssaidi@eecs.umich.edu sys.exit(1) 1553881Ssaidi@eecs.umich.edu 1563569Sgblack@eecs.umich.edu 1573569Sgblack@eecs.umich.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1583881Ssaidi@eecs.umich.eduCPUClass.numThreads = numThreads 1593804Ssaidi@eecs.umich.edu 1603881Ssaidi@eecs.umich.edu# Check -- do not allow SMT with multiple CPUs 1613826Ssaidi@eecs.umich.eduif options.smt and options.num_cpus > 1: 1623881Ssaidi@eecs.umich.edu fatal("You cannot use SMT with multiple CPUs!") 1633881Ssaidi@eecs.umich.edu 1643881Ssaidi@eecs.umich.edunp = options.num_cpus 1653907Ssaidi@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1663907Ssaidi@eecs.umich.edu mem_mode = test_mem_mode, 1673929Ssaidi@eecs.umich.edu mem_ranges = [AddrRange(options.mem_size)], 1683929Ssaidi@eecs.umich.edu cache_line_size = options.cacheline_size) 1693907Ssaidi@eecs.umich.edu 1703907Ssaidi@eecs.umich.edu# Create a top-level voltage domain 1713804Ssaidi@eecs.umich.edusystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1723804Ssaidi@eecs.umich.edu 1733881Ssaidi@eecs.umich.edu# Create a source clock for the system and set the clock period 1743804Ssaidi@eecs.umich.edusystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 1753804Ssaidi@eecs.umich.edu voltage_domain = system.voltage_domain) 1763804Ssaidi@eecs.umich.edu 1773804Ssaidi@eecs.umich.edu# Create a CPU voltage domain 1783804Ssaidi@eecs.umich.edusystem.cpu_voltage_domain = VoltageDomain() 1793804Ssaidi@eecs.umich.edu 1803804Ssaidi@eecs.umich.edu# Create a separate clock domain for the CPUs 1813569Sgblack@eecs.umich.edusystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1823863Ssaidi@eecs.umich.edu voltage_domain = 1833863Ssaidi@eecs.umich.edu system.cpu_voltage_domain) 1843804Ssaidi@eecs.umich.edu 1855555Snate@binkert.org# All cpus belong to a common cpu_clk_domain, therefore running at a common 1865555Snate@binkert.org# frequency. 1873804Ssaidi@eecs.umich.edufor cpu in system.cpu: 1883804Ssaidi@eecs.umich.edu cpu.clk_domain = system.cpu_clk_domain 1893804Ssaidi@eecs.umich.edu 1903804Ssaidi@eecs.umich.edu# Sanity check 1913804Ssaidi@eecs.umich.eduif options.fastmem: 1923569Sgblack@eecs.umich.edu if CPUClass != AtomicSimpleCPU: 1933804Ssaidi@eecs.umich.edu fatal("Fastmem can only be used with atomic CPU!") 1943804Ssaidi@eecs.umich.edu if (options.caches or options.l2cache): 1953804Ssaidi@eecs.umich.edu fatal("You cannot use fastmem in combination with caches!") 1965555Snate@binkert.org 1975555Snate@binkert.orgif options.simpoint_profile: 1983804Ssaidi@eecs.umich.edu if not options.fastmem: 1993804Ssaidi@eecs.umich.edu # Atomic CPU checked with fastmem option already 2003804Ssaidi@eecs.umich.edu fatal("SimPoint generation should be done with atomic cpu and fastmem") 2013804Ssaidi@eecs.umich.edu if np > 1: 2023804Ssaidi@eecs.umich.edu fatal("SimPoint generation not supported with more than one CPUs") 2033811Ssaidi@eecs.umich.edu 2043811Ssaidi@eecs.umich.edufor i in xrange(np): 2053804Ssaidi@eecs.umich.edu if options.smt: 2063804Ssaidi@eecs.umich.edu system.cpu[i].workload = multiprocesses 2075312Sgblack@eecs.umich.edu elif len(multiprocesses) == 1: 2083804Ssaidi@eecs.umich.edu system.cpu[i].workload = multiprocesses[0] 2093804Ssaidi@eecs.umich.edu else: 2103804Ssaidi@eecs.umich.edu system.cpu[i].workload = multiprocesses[i] 2113804Ssaidi@eecs.umich.edu 2123804Ssaidi@eecs.umich.edu if options.fastmem: 2133804Ssaidi@eecs.umich.edu system.cpu[i].fastmem = True 2143804Ssaidi@eecs.umich.edu 2153811Ssaidi@eecs.umich.edu if options.simpoint_profile: 2163804Ssaidi@eecs.umich.edu system.cpu[i].simpoint_profile = True 2173804Ssaidi@eecs.umich.edu system.cpu[i].simpoint_interval = options.simpoint_interval 2183804Ssaidi@eecs.umich.edu 2193804Ssaidi@eecs.umich.edu if options.checker: 2203804Ssaidi@eecs.umich.edu system.cpu[i].addCheckerCpu() 2213826Ssaidi@eecs.umich.edu 2223826Ssaidi@eecs.umich.edu system.cpu[i].createThreads() 2234070Ssaidi@eecs.umich.edu 2245555Snate@binkert.orgif options.ruby: 2255555Snate@binkert.org if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 2264070Ssaidi@eecs.umich.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 2273804Ssaidi@eecs.umich.edu sys.exit(1) 2283804Ssaidi@eecs.umich.edu 2293804Ssaidi@eecs.umich.edu # Use SimpleMemory with the null option since this memory is only used 2303804Ssaidi@eecs.umich.edu # for determining which addresses are within the range of the memory. 2313804Ssaidi@eecs.umich.edu # No space allocation is required. 2323804Ssaidi@eecs.umich.edu system.physmem = SimpleMemory(range=AddrRange(options.mem_size), 2333804Ssaidi@eecs.umich.edu null = True) 2343804Ssaidi@eecs.umich.edu options.use_map = True 2353804Ssaidi@eecs.umich.edu Ruby.create_system(options, system) 2363804Ssaidi@eecs.umich.edu assert(options.num_cpus == len(system.ruby._cpu_ports)) 2373804Ssaidi@eecs.umich.edu 2383804Ssaidi@eecs.umich.edu system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 2393826Ssaidi@eecs.umich.edu voltage_domain = system.voltage_domain) 2403826Ssaidi@eecs.umich.edu for i in xrange(np): 2413826Ssaidi@eecs.umich.edu ruby_port = system.ruby._cpu_ports[i] 2423863Ssaidi@eecs.umich.edu 2433826Ssaidi@eecs.umich.edu # Create the interrupt controller and connect its ports to Ruby 2443826Ssaidi@eecs.umich.edu # Note that the interrupt controller is always present but only 2453826Ssaidi@eecs.umich.edu # in x86 does it have message ports that need to be connected 2463826Ssaidi@eecs.umich.edu system.cpu[i].createInterruptController() 2473826Ssaidi@eecs.umich.edu 2483826Ssaidi@eecs.umich.edu # Connect the cpu's cache ports to Ruby 2493826Ssaidi@eecs.umich.edu system.cpu[i].icache_port = ruby_port.slave 2503826Ssaidi@eecs.umich.edu system.cpu[i].dcache_port = ruby_port.slave 2513826Ssaidi@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 2523804Ssaidi@eecs.umich.edu system.cpu[i].interrupts.pio = ruby_port.master 2533804Ssaidi@eecs.umich.edu system.cpu[i].interrupts.int_master = ruby_port.slave 2543804Ssaidi@eecs.umich.edu system.cpu[i].interrupts.int_slave = ruby_port.master 2553804Ssaidi@eecs.umich.edu system.cpu[i].itb.walker.port = ruby_port.slave 2563804Ssaidi@eecs.umich.edu system.cpu[i].dtb.walker.port = ruby_port.slave 2573804Ssaidi@eecs.umich.eduelse: 2583804Ssaidi@eecs.umich.edu MemClass = Simulation.setMemClass(options) 2593863Ssaidi@eecs.umich.edu system.membus = CoherentBus() 2603863Ssaidi@eecs.umich.edu system.system_port = system.membus.slave 2613863Ssaidi@eecs.umich.edu CacheConfig.config_cache(options, system) 2623836Ssaidi@eecs.umich.edu MemConfig.config_mem(options, system) 2633836Ssaidi@eecs.umich.edu 2643804Ssaidi@eecs.umich.eduroot = Root(full_system = False, system = system) 2653804Ssaidi@eecs.umich.eduSimulation.run(options, root, system, FutureClass) 2665312Sgblack@eecs.umich.edu