se.py revision 10118
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt 403005Sstever@eecs.umich.edu 412710SN/A# Simple test script 422710SN/A# 433005Sstever@eecs.umich.edu# "m5 test.py" 442889SN/A 456654Snate@binkert.orgimport optparse 466654Snate@binkert.orgimport sys 479907Snilay@cs.wisc.eduimport os 486654Snate@binkert.org 492667SN/Aimport m5 506654Snate@binkert.orgfrom m5.defines import buildEnv 516654Snate@binkert.orgfrom m5.objects import * 526654Snate@binkert.orgfrom m5.util import addToPath, fatal 535457Ssaidi@eecs.umich.edu 546654Snate@binkert.orgaddToPath('../common') 558169SLisa.Hsu@amd.comaddToPath('../ruby') 568169SLisa.Hsu@amd.com 578920Snilay@cs.wisc.eduimport Options 588169SLisa.Hsu@amd.comimport Ruby 593395Shsul@eecs.umich.eduimport Simulation 606981SLisa.Hsu@amd.comimport CacheConfig 619836Sandreas.hansson@arm.comimport MemConfig 623448Shsul@eecs.umich.edufrom Caches import * 635369Ssaidi@eecs.umich.edufrom cpu2000 import * 643394Shsul@eecs.umich.edu 659197Snilay@cs.wisc.edudef get_processes(options): 669197Snilay@cs.wisc.edu """Interprets provided options and returns a list of processes""" 679197Snilay@cs.wisc.edu 689197Snilay@cs.wisc.edu multiprocesses = [] 699197Snilay@cs.wisc.edu inputs = [] 709197Snilay@cs.wisc.edu outputs = [] 719197Snilay@cs.wisc.edu errouts = [] 729197Snilay@cs.wisc.edu pargs = [] 739197Snilay@cs.wisc.edu 749197Snilay@cs.wisc.edu workloads = options.cmd.split(';') 759197Snilay@cs.wisc.edu if options.input != "": 769197Snilay@cs.wisc.edu inputs = options.input.split(';') 779197Snilay@cs.wisc.edu if options.output != "": 789197Snilay@cs.wisc.edu outputs = options.output.split(';') 799197Snilay@cs.wisc.edu if options.errout != "": 809197Snilay@cs.wisc.edu errouts = options.errout.split(';') 819197Snilay@cs.wisc.edu if options.options != "": 829197Snilay@cs.wisc.edu pargs = options.options.split(';') 839197Snilay@cs.wisc.edu 849197Snilay@cs.wisc.edu idx = 0 859197Snilay@cs.wisc.edu for wrkld in workloads: 869197Snilay@cs.wisc.edu process = LiveProcess() 879197Snilay@cs.wisc.edu process.executable = wrkld 889907Snilay@cs.wisc.edu process.cwd = os.getcwd() 899197Snilay@cs.wisc.edu 909197Snilay@cs.wisc.edu if len(pargs) > idx: 919217Snilay@cs.wisc.edu process.cmd = [wrkld] + pargs[idx].split() 929197Snilay@cs.wisc.edu else: 939197Snilay@cs.wisc.edu process.cmd = [wrkld] 949197Snilay@cs.wisc.edu 959197Snilay@cs.wisc.edu if len(inputs) > idx: 969197Snilay@cs.wisc.edu process.input = inputs[idx] 979197Snilay@cs.wisc.edu if len(outputs) > idx: 989197Snilay@cs.wisc.edu process.output = outputs[idx] 999197Snilay@cs.wisc.edu if len(errouts) > idx: 1009197Snilay@cs.wisc.edu process.errout = errouts[idx] 1019197Snilay@cs.wisc.edu 1029197Snilay@cs.wisc.edu multiprocesses.append(process) 1039197Snilay@cs.wisc.edu idx += 1 1049197Snilay@cs.wisc.edu 1059197Snilay@cs.wisc.edu if options.smt: 1069197Snilay@cs.wisc.edu assert(options.cpu_type == "detailed" or options.cpu_type == "inorder") 1079197Snilay@cs.wisc.edu return multiprocesses, idx 1089197Snilay@cs.wisc.edu else: 1099197Snilay@cs.wisc.edu return multiprocesses, 1 1109197Snilay@cs.wisc.edu 1119197Snilay@cs.wisc.edu 1122957SN/Aparser = optparse.OptionParser() 1138920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 1148920Snilay@cs.wisc.eduOptions.addSEOptions(parser) 1152957SN/A 1168862Snilay@cs.wisc.eduif '--ruby' in sys.argv: 1178862Snilay@cs.wisc.edu Ruby.define_options(parser) 1188467Snilay@cs.wisc.edu 1192957SN/A(options, args) = parser.parse_args() 1202957SN/A 1212957SN/Aif args: 1222957SN/A print "Error: script doesn't take any positional arguments" 1232957SN/A sys.exit(1) 1242957SN/A 1258167SLisa.Hsu@amd.commultiprocesses = [] 1269197Snilay@cs.wisc.edunumThreads = 1 1278167SLisa.Hsu@amd.com 1285369Ssaidi@eecs.umich.eduif options.bench: 1298167SLisa.Hsu@amd.com apps = options.bench.split("-") 1308167SLisa.Hsu@amd.com if len(apps) != options.num_cpus: 1318167SLisa.Hsu@amd.com print "number of benchmarks not equal to set num_cpus!" 1328167SLisa.Hsu@amd.com sys.exit(1) 1338167SLisa.Hsu@amd.com 1348167SLisa.Hsu@amd.com for app in apps: 1358167SLisa.Hsu@amd.com try: 1368168SLisa.Hsu@amd.com if buildEnv['TARGET_ISA'] == 'alpha': 13710037SARM gem5 Developers exec("workload = %s('alpha', 'tru64', '%s')" % ( 13810037SARM gem5 Developers app, options.spec_input)) 13910037SARM gem5 Developers elif buildEnv['TARGET_ISA'] == 'arm': 14010037SARM gem5 Developers exec("workload = %s('arm_%s', 'linux', '%s')" % ( 14110037SARM gem5 Developers app, options.arm_iset, options.spec_input)) 1428168SLisa.Hsu@amd.com else: 14310037SARM gem5 Developers exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 14410037SARM gem5 Developers app, options.spec_input)) 1458167SLisa.Hsu@amd.com multiprocesses.append(workload.makeLiveProcess()) 1468167SLisa.Hsu@amd.com except: 14710118Snilay@cs.wisc.edu print >>sys.stderr, "Unable to find workload for %s: %s" % ( 14810118Snilay@cs.wisc.edu buildEnv['TARGET_ISA'], app) 1495369Ssaidi@eecs.umich.edu sys.exit(1) 1508920Snilay@cs.wisc.eduelif options.cmd: 1519197Snilay@cs.wisc.edu multiprocesses, numThreads = get_processes(options) 1528920Snilay@cs.wisc.eduelse: 1538920Snilay@cs.wisc.edu print >> sys.stderr, "No workload specified. Exiting!\n" 1548920Snilay@cs.wisc.edu sys.exit(1) 1555369Ssaidi@eecs.umich.edu 1565369Ssaidi@eecs.umich.edu 1578718Snilay@cs.wisc.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1589197Snilay@cs.wisc.eduCPUClass.numThreads = numThreads 1599197Snilay@cs.wisc.edu 1609665Sandreas.hansson@arm.comMemClass = Simulation.setMemClass(options) 1619665Sandreas.hansson@arm.com 1629197Snilay@cs.wisc.edu# Check -- do not allow SMT with multiple CPUs 1639197Snilay@cs.wisc.eduif options.smt and options.num_cpus > 1: 1649197Snilay@cs.wisc.edu fatal("You cannot use SMT with multiple CPUs!") 1653005Sstever@eecs.umich.edu 1663395Shsul@eecs.umich.edunp = options.num_cpus 1673395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1689793Sakash.bagdia@arm.com mem_mode = test_mem_mode, 1699836Sandreas.hansson@arm.com mem_ranges = [AddrRange(options.mem_size)], 1709815SAndreas Hansson <andreas.hansson> cache_line_size = options.cacheline_size) 1719793Sakash.bagdia@arm.com 1729827Sakash.bagdia@arm.com# Create a top-level voltage domain 1739827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1749827Sakash.bagdia@arm.com 1759827Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period 1769827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 1779827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 1789827Sakash.bagdia@arm.com 1799827Sakash.bagdia@arm.com# Create a CPU voltage domain 1809827Sakash.bagdia@arm.comsystem.cpu_voltage_domain = VoltageDomain() 1819827Sakash.bagdia@arm.com 1829793Sakash.bagdia@arm.com# Create a separate clock domain for the CPUs 1839827Sakash.bagdia@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1849827Sakash.bagdia@arm.com voltage_domain = 1859827Sakash.bagdia@arm.com system.cpu_voltage_domain) 1869793Sakash.bagdia@arm.com 1879793Sakash.bagdia@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 1889793Sakash.bagdia@arm.com# frequency. 1899793Sakash.bagdia@arm.comfor cpu in system.cpu: 1909793Sakash.bagdia@arm.com cpu.clk_domain = system.cpu_clk_domain 1913395Shsul@eecs.umich.edu 1928926Sandreas.hansson@arm.com# Sanity check 1939317Sandreas.hansson@arm.comif options.fastmem: 1949317Sandreas.hansson@arm.com if CPUClass != AtomicSimpleCPU: 1959317Sandreas.hansson@arm.com fatal("Fastmem can only be used with atomic CPU!") 1969317Sandreas.hansson@arm.com if (options.caches or options.l2cache): 1979317Sandreas.hansson@arm.com fatal("You cannot use fastmem in combination with caches!") 1988926Sandreas.hansson@arm.com 1999647Sdam.sunwoo@arm.comif options.simpoint_profile: 2009647Sdam.sunwoo@arm.com if not options.fastmem: 2019647Sdam.sunwoo@arm.com # Atomic CPU checked with fastmem option already 2029647Sdam.sunwoo@arm.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 2039647Sdam.sunwoo@arm.com if np > 1: 2049647Sdam.sunwoo@arm.com fatal("SimPoint generation not supported with more than one CPUs") 2059647Sdam.sunwoo@arm.com 2063395Shsul@eecs.umich.edufor i in xrange(np): 2079197Snilay@cs.wisc.edu if options.smt: 2089197Snilay@cs.wisc.edu system.cpu[i].workload = multiprocesses 2099197Snilay@cs.wisc.edu elif len(multiprocesses) == 1: 2108957Sjayneel@cs.wisc.edu system.cpu[i].workload = multiprocesses[0] 2118957Sjayneel@cs.wisc.edu else: 2128957Sjayneel@cs.wisc.edu system.cpu[i].workload = multiprocesses[i] 2133005Sstever@eecs.umich.edu 2144968Sacolyte@umich.edu if options.fastmem: 2159006Sandreas.hansson@arm.com system.cpu[i].fastmem = True 2164968Sacolyte@umich.edu 2179647Sdam.sunwoo@arm.com if options.simpoint_profile: 2189647Sdam.sunwoo@arm.com system.cpu[i].simpoint_profile = True 2199647Sdam.sunwoo@arm.com system.cpu[i].simpoint_interval = options.simpoint_interval 2209647Sdam.sunwoo@arm.com 2218887Sgeoffrey.blake@arm.com if options.checker: 2228887Sgeoffrey.blake@arm.com system.cpu[i].addCheckerCpu() 2238887Sgeoffrey.blake@arm.com 2249384SAndreas.Sandberg@arm.com system.cpu[i].createThreads() 2259384SAndreas.Sandberg@arm.com 2268887Sgeoffrey.blake@arm.comif options.ruby: 2278896Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 2288896Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 2298896Snilay@cs.wisc.edu sys.exit(1) 2308896Snilay@cs.wisc.edu 2319577Snilay@cs.wisc.edu # Set the option for physmem so that it is not allocated any space 2329836Sandreas.hansson@arm.com system.physmem = MemClass(range=AddrRange(options.mem_size), 2339836Sandreas.hansson@arm.com null = True) 23410092Snilay@cs.wisc.edu options.use_map = True 23510117Snilay@cs.wisc.edu Ruby.create_system(options, system) 2368887Sgeoffrey.blake@arm.com assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 2378896Snilay@cs.wisc.edu 2388896Snilay@cs.wisc.edu for i in xrange(np): 2398896Snilay@cs.wisc.edu ruby_port = system.ruby._cpu_ruby_ports[i] 2408896Snilay@cs.wisc.edu 2418896Snilay@cs.wisc.edu # Create the interrupt controller and connect its ports to Ruby 2429268Smalek.musleh@gmail.com # Note that the interrupt controller is always present but only 2439268Smalek.musleh@gmail.com # in x86 does it have message ports that need to be connected 2448896Snilay@cs.wisc.edu system.cpu[i].createInterruptController() 2458896Snilay@cs.wisc.edu 2468896Snilay@cs.wisc.edu # Connect the cpu's cache ports to Ruby 2478896Snilay@cs.wisc.edu system.cpu[i].icache_port = ruby_port.slave 2488896Snilay@cs.wisc.edu system.cpu[i].dcache_port = ruby_port.slave 2499222Shestness@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'x86': 2509268Smalek.musleh@gmail.com system.cpu[i].interrupts.pio = ruby_port.master 2519268Smalek.musleh@gmail.com system.cpu[i].interrupts.int_master = ruby_port.slave 2529268Smalek.musleh@gmail.com system.cpu[i].interrupts.int_slave = ruby_port.master 2539222Shestness@cs.wisc.edu system.cpu[i].itb.walker.port = ruby_port.slave 2549222Shestness@cs.wisc.edu system.cpu[i].dtb.walker.port = ruby_port.slave 2558887Sgeoffrey.blake@arm.comelse: 2569756Snilay@cs.wisc.edu system.membus = CoherentBus() 2578887Sgeoffrey.blake@arm.com system.system_port = system.membus.slave 2588887Sgeoffrey.blake@arm.com CacheConfig.config_cache(options, system) 2599836Sandreas.hansson@arm.com MemConfig.config_mem(options, system) 2608887Sgeoffrey.blake@arm.com 2618801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 2623481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass) 263