ruby_random_test.py revision 13774:a1be2a0c55f2
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31from __future__ import print_function 32from __future__ import absolute_import 33 34import m5 35from m5.objects import * 36from m5.defines import buildEnv 37from m5.util import addToPath 38import os, optparse, sys 39 40addToPath('../') 41 42from common import Options 43from ruby import Ruby 44 45# Get paths we might need. It's expected this file is in m5/configs/example. 46config_path = os.path.dirname(os.path.abspath(__file__)) 47config_root = os.path.dirname(config_path) 48m5_root = os.path.dirname(config_root) 49 50parser = optparse.OptionParser() 51Options.addNoISAOptions(parser) 52 53parser.add_option("--maxloads", metavar="N", default=100, 54 help="Stop after N loads") 55parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 56 help="Wakeup every N cycles") 57 58# 59# Add the ruby specific and protocol specific options 60# 61Ruby.define_options(parser) 62 63exec(compile( \ 64 open(os.path.join(config_root, "common", "Options.py")).read(), \ 65 os.path.join(config_root, "common", "Options.py"), 'exec')) 66 67(options, args) = parser.parse_args() 68 69# 70# Set the default cache size and associativity to be very small to encourage 71# races between requests and writebacks. 72# 73options.l1d_size="256B" 74options.l1i_size="256B" 75options.l2_size="512B" 76options.l3_size="1kB" 77options.l1d_assoc=2 78options.l1i_assoc=2 79options.l2_assoc=2 80options.l3_assoc=2 81 82if args: 83 print("Error: script doesn't take any positional arguments") 84 sys.exit(1) 85 86# 87# Create the ruby random tester 88# 89 90# Check the protocol 91check_flush = False 92if buildEnv['PROTOCOL'] == 'MOESI_hammer': 93 check_flush = True 94 95tester = RubyTester(check_flush = check_flush, 96 checks_to_complete = options.maxloads, 97 wakeup_frequency = options.wakeup_freq) 98 99# 100# Create the M5 system. Note that the Memory Object isn't 101# actually used by the rubytester, but is included to support the 102# M5 memory size == Ruby memory size checks 103# 104system = System(cpu = tester, mem_ranges = [AddrRange(options.mem_size)]) 105 106# Create a top-level voltage domain and clock domain 107system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 108 109system.clk_domain = SrcClockDomain(clock = options.sys_clock, 110 voltage_domain = system.voltage_domain) 111 112Ruby.create_system(options, False, system) 113 114# Create a seperate clock domain for Ruby 115system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 116 voltage_domain = system.voltage_domain) 117 118assert(options.num_cpus == len(system.ruby._cpu_ports)) 119 120tester.num_cpus = len(system.ruby._cpu_ports) 121 122# 123# The tester is most effective when randomization is turned on and 124# artifical delay is randomly inserted on messages 125# 126system.ruby.randomization = True 127 128for ruby_port in system.ruby._cpu_ports: 129 # 130 # Tie the ruby tester ports to the ruby cpu read and write ports 131 # 132 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: 133 tester.cpuInstDataPort = ruby_port.slave 134 elif ruby_port.support_data_reqs: 135 tester.cpuDataPort = ruby_port.slave 136 elif ruby_port.support_inst_reqs: 137 tester.cpuInstPort = ruby_port.slave 138 139 # Do not automatically retry stalled Ruby requests 140 ruby_port.no_retry_on_stall = True 141 142 # 143 # Tell each sequencer this is the ruby tester so that it 144 # copies the subblock back to the checker 145 # 146 ruby_port.using_ruby_tester = True 147 148# ----------------------- 149# run simulation 150# ----------------------- 151 152root = Root( full_system = False, system = system ) 153root.system.mem_mode = 'timing' 154 155# Not much point in this being higher than the L1 latency 156m5.ticks.setGlobalFrequency('1ns') 157 158# instantiate configuration 159m5.instantiate() 160 161# simulate until program terminates 162exit_event = m5.simulate(options.abs_max_tick) 163 164print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 165