ruby_random_test.py revision 13731
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31from __future__ import print_function 32 33import m5 34from m5.objects import * 35from m5.defines import buildEnv 36from m5.util import addToPath 37import os, optparse, sys 38 39addToPath('../') 40 41from common import Options 42from ruby import Ruby 43 44# Get paths we might need. It's expected this file is in m5/configs/example. 45config_path = os.path.dirname(os.path.abspath(__file__)) 46config_root = os.path.dirname(config_path) 47m5_root = os.path.dirname(config_root) 48 49parser = optparse.OptionParser() 50Options.addNoISAOptions(parser) 51 52parser.add_option("--maxloads", metavar="N", default=100, 53 help="Stop after N loads") 54parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 55 help="Wakeup every N cycles") 56 57# 58# Add the ruby specific and protocol specific options 59# 60Ruby.define_options(parser) 61 62exec(compile( \ 63 open(os.path.join(config_root, "common", "Options.py")).read(), \ 64 os.path.join(config_root, "common", "Options.py"), 'exec')) 65 66(options, args) = parser.parse_args() 67 68# 69# Set the default cache size and associativity to be very small to encourage 70# races between requests and writebacks. 71# 72options.l1d_size="256B" 73options.l1i_size="256B" 74options.l2_size="512B" 75options.l3_size="1kB" 76options.l1d_assoc=2 77options.l1i_assoc=2 78options.l2_assoc=2 79options.l3_assoc=2 80 81if args: 82 print("Error: script doesn't take any positional arguments") 83 sys.exit(1) 84 85# 86# Create the ruby random tester 87# 88 89# Check the protocol 90check_flush = False 91if buildEnv['PROTOCOL'] == 'MOESI_hammer': 92 check_flush = True 93 94tester = RubyTester(check_flush = check_flush, 95 checks_to_complete = options.maxloads, 96 wakeup_frequency = options.wakeup_freq) 97 98# 99# Create the M5 system. Note that the Memory Object isn't 100# actually used by the rubytester, but is included to support the 101# M5 memory size == Ruby memory size checks 102# 103system = System(cpu = tester, mem_ranges = [AddrRange(options.mem_size)]) 104 105# Create a top-level voltage domain and clock domain 106system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 107 108system.clk_domain = SrcClockDomain(clock = options.sys_clock, 109 voltage_domain = system.voltage_domain) 110 111Ruby.create_system(options, False, system) 112 113# Create a seperate clock domain for Ruby 114system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 115 voltage_domain = system.voltage_domain) 116 117assert(options.num_cpus == len(system.ruby._cpu_ports)) 118 119tester.num_cpus = len(system.ruby._cpu_ports) 120 121# 122# The tester is most effective when randomization is turned on and 123# artifical delay is randomly inserted on messages 124# 125system.ruby.randomization = True 126 127for ruby_port in system.ruby._cpu_ports: 128 # 129 # Tie the ruby tester ports to the ruby cpu read and write ports 130 # 131 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: 132 tester.cpuInstDataPort = ruby_port.slave 133 elif ruby_port.support_data_reqs: 134 tester.cpuDataPort = ruby_port.slave 135 elif ruby_port.support_inst_reqs: 136 tester.cpuInstPort = ruby_port.slave 137 138 # Do not automatically retry stalled Ruby requests 139 ruby_port.no_retry_on_stall = True 140 141 # 142 # Tell each sequencer this is the ruby tester so that it 143 # copies the subblock back to the checker 144 # 145 ruby_port.using_ruby_tester = True 146 147# ----------------------- 148# run simulation 149# ----------------------- 150 151root = Root( full_system = False, system = system ) 152root.system.mem_mode = 'timing' 153 154# Not much point in this being higher than the L1 latency 155m5.ticks.setGlobalFrequency('1ns') 156 157# instantiate configuration 158m5.instantiate() 159 160# simulate until program terminates 161exit_event = m5.simulate(options.abs_max_tick) 162 163print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 164