ruby_random_test.py revision 11682:612f75cf36a0 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29#          Brad Beckmann
30
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from m5.util import addToPath
35import os, optparse, sys
36
37addToPath('../')
38
39from common import Options
40from ruby import Ruby
41
42# Get paths we might need.  It's expected this file is in m5/configs/example.
43config_path = os.path.dirname(os.path.abspath(__file__))
44config_root = os.path.dirname(config_path)
45m5_root = os.path.dirname(config_root)
46
47parser = optparse.OptionParser()
48Options.addCommonOptions(parser)
49
50parser.add_option("--maxloads", metavar="N", default=100,
51                  help="Stop after N loads")
52parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
53                  help="Wakeup every N cycles")
54
55#
56# Add the ruby specific and protocol specific options
57#
58Ruby.define_options(parser)
59
60execfile(os.path.join(config_root, "common", "Options.py"))
61
62(options, args) = parser.parse_args()
63
64#
65# Set the default cache size and associativity to be very small to encourage
66# races between requests and writebacks.
67#
68options.l1d_size="256B"
69options.l1i_size="256B"
70options.l2_size="512B"
71options.l3_size="1kB"
72options.l1d_assoc=2
73options.l1i_assoc=2
74options.l2_assoc=2
75options.l3_assoc=2
76
77if args:
78     print "Error: script doesn't take any positional arguments"
79     sys.exit(1)
80
81#
82# Create the ruby random tester
83#
84
85# Check the protocol
86check_flush = False
87if buildEnv['PROTOCOL'] == 'MOESI_hammer':
88    check_flush = True
89
90tester = RubyTester(check_flush = check_flush,
91                    checks_to_complete = options.maxloads,
92                    wakeup_frequency = options.wakeup_freq)
93
94#
95# Create the M5 system.  Note that the Memory Object isn't
96# actually used by the rubytester, but is included to support the
97# M5 memory size == Ruby memory size checks
98#
99system = System(cpu = tester, mem_ranges = [AddrRange(options.mem_size)])
100
101# Create a top-level voltage domain and clock domain
102system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
103
104system.clk_domain = SrcClockDomain(clock = options.sys_clock,
105                                   voltage_domain = system.voltage_domain)
106
107Ruby.create_system(options, False, system)
108
109# Create a seperate clock domain for Ruby
110system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
111                                        voltage_domain = system.voltage_domain)
112
113assert(options.num_cpus == len(system.ruby._cpu_ports))
114
115tester.num_cpus = len(system.ruby._cpu_ports)
116
117#
118# The tester is most effective when randomization is turned on and
119# artifical delay is randomly inserted on messages
120#
121system.ruby.randomization = True
122
123for ruby_port in system.ruby._cpu_ports:
124    #
125    # Tie the ruby tester ports to the ruby cpu read and write ports
126    #
127    if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
128        tester.cpuInstDataPort = ruby_port.slave
129    elif ruby_port.support_data_reqs:
130        tester.cpuDataPort = ruby_port.slave
131    elif ruby_port.support_inst_reqs:
132        tester.cpuInstPort = ruby_port.slave
133
134    # Do not automatically retry stalled Ruby requests
135    ruby_port.no_retry_on_stall = True
136
137    #
138    # Tell each sequencer this is the ruby tester so that it
139    # copies the subblock back to the checker
140    #
141    ruby_port.using_ruby_tester = True
142
143# -----------------------
144# run simulation
145# -----------------------
146
147root = Root( full_system = False, system = system )
148root.system.mem_mode = 'timing'
149
150# Not much point in this being higher than the L1 latency
151m5.ticks.setGlobalFrequency('1ns')
152
153# instantiate configuration
154m5.instantiate()
155
156# simulate until program terminates
157exit_event = m5.simulate(options.abs_max_tick)
158
159print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
160