ruby_random_test.py revision 10083:2beea2a439b4 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29#          Brad Beckmann
30
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from m5.util import addToPath
35import os, optparse, sys
36addToPath('../common')
37addToPath('../ruby')
38addToPath('../topologies')
39
40import Options
41import Ruby
42
43# Get paths we might need.  It's expected this file is in m5/configs/example.
44config_path = os.path.dirname(os.path.abspath(__file__))
45config_root = os.path.dirname(config_path)
46m5_root = os.path.dirname(config_root)
47
48parser = optparse.OptionParser()
49Options.addCommonOptions(parser)
50
51parser.add_option("--maxloads", metavar="N", default=100,
52                  help="Stop after N loads")
53parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
54                  help="Wakeup every N cycles")
55
56#
57# Add the ruby specific and protocol specific options
58#
59Ruby.define_options(parser)
60
61execfile(os.path.join(config_root, "common", "Options.py"))
62
63(options, args) = parser.parse_args()
64
65#
66# Set the default cache size and associativity to be very small to encourage
67# races between requests and writebacks.
68#
69options.l1d_size="256B"
70options.l1i_size="256B"
71options.l2_size="512B"
72options.l3_size="1kB"
73options.l1d_assoc=2
74options.l1i_assoc=2
75options.l2_assoc=2
76options.l3_assoc=2
77
78if args:
79     print "Error: script doesn't take any positional arguments"
80     sys.exit(1)
81
82#
83# Create the ruby random tester
84#
85
86# Check the protocol
87check_flush = False
88if buildEnv['PROTOCOL'] == 'MOESI_hammer':
89    check_flush = True
90
91tester = RubyTester(check_flush = check_flush,
92                    checks_to_complete = options.maxloads,
93                    wakeup_frequency = options.wakeup_freq)
94
95#
96# Create the M5 system.  Note that the Memory Object isn't
97# actually used by the rubytester, but is included to support the
98# M5 memory size == Ruby memory size checks
99#
100system = System(tester = tester, physmem = SimpleMemory(),
101                mem_ranges = [AddrRange(options.mem_size)])
102
103# Create a top-level voltage domain and clock domain
104system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
105
106system.clk_domain = SrcClockDomain(clock = options.sys_clock,
107                                   voltage_domain = system.voltage_domain)
108
109Ruby.create_system(options, system)
110
111# Create a seperate clock domain for Ruby
112system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
113                                        voltage_domain = system.voltage_domain)
114
115assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
116
117tester.num_cpus = len(system.ruby._cpu_ruby_ports)
118
119#
120# The tester is most effective when randomization is turned on and
121# artifical delay is randomly inserted on messages
122#
123system.ruby.randomization = True
124
125for ruby_port in system.ruby._cpu_ruby_ports:
126    #
127    # Tie the ruby tester ports to the ruby cpu read and write ports
128    #
129    if ruby_port.support_data_reqs:
130         tester.cpuDataPort = ruby_port.slave
131    if ruby_port.support_inst_reqs:
132         tester.cpuInstPort = ruby_port.slave
133
134    #
135    # Tell each sequencer this is the ruby tester so that it
136    # copies the subblock back to the checker
137    #
138    ruby_port.using_ruby_tester = True
139
140    #
141    # Ruby doesn't need the backing image of memory when running with
142    # the tester.
143    #
144    ruby_port.access_phys_mem = False
145
146# -----------------------
147# run simulation
148# -----------------------
149
150root = Root( full_system = False, system = system )
151root.system.mem_mode = 'timing'
152
153# Not much point in this being higher than the L1 latency
154m5.ticks.setGlobalFrequency('1ns')
155
156# instantiate configuration
157m5.instantiate()
158
159# simulate until program terminates
160exit_event = m5.simulate(options.abs_max_tick)
161
162print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
163