ruby_random_test.py revision 8845
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
21762SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc.
32SN/A# All rights reserved.
42SN/A#
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62SN/A# modification, are permitted provided that the following conditions are
72SN/A# met: redistributions of source code must retain the above copyright
82SN/A# notice, this list of conditions and the following disclaimer;
92SN/A# redistributions in binary form must reproduce the above copyright
102SN/A# notice, this list of conditions and the following disclaimer in the
112SN/A# documentation and/or other materials provided with the distribution;
122SN/A# neither the name of the copyright holders nor the names of its
132SN/A# contributors may be used to endorse or promote products derived from
142SN/A# this software without specific prior written permission.
152SN/A#
162SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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262SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu#
282665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski
292SN/A#          Brad Beckmann
302SN/A
312439SN/Aimport m5
32146SN/Afrom m5.objects import *
33146SN/Afrom m5.defines import buildEnv
34146SN/Afrom m5.util import addToPath
35146SN/Aimport os, optparse, sys
36146SN/AaddToPath('../common')
37146SN/AaddToPath('../ruby')
381717SN/A
39146SN/Aimport Ruby
401717SN/A
412190SN/A# Get paths we might need.  It's expected this file is in m5/configs/example.
422680Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__))
43146SN/Aconfig_root = os.path.dirname(config_path)
441977SN/Am5_root = os.path.dirname(config_root)
451717SN/A
462623SN/Aparser = optparse.OptionParser()
471717SN/A
48146SN/Aparser.add_option("-l", "--checks", metavar="N", default=100,
491917SN/A                  help="Stop after N checks (loads)")
502592SN/Aparser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
512036SN/A                  help="Wakeup every N cycles")
52146SN/A
53146SN/A#
5456SN/A# Add the ruby specific and protocol specific options
5556SN/A#
5656SN/ARuby.define_options(parser)
57695SN/A
582SN/Aexecfile(os.path.join(config_root, "common", "Options.py"))
591858SN/A
6056SN/A(options, args) = parser.parse_args()
61146SN/A
622171SN/A#
632170SN/A# Set the default cache size and associativity to be very small to encourage
642170SN/A# races between requests and writebacks.
65146SN/A#
662462SN/Aoptions.l1d_size="256B"
67146SN/Aoptions.l1i_size="256B"
682SN/Aoptions.l2_size="512B"
692SN/Aoptions.l3_size="1kB"
702449SN/Aoptions.l1d_assoc=2
711355SN/Aoptions.l1i_assoc=2
722623SN/Aoptions.l2_assoc=2
732623SN/Aoptions.l3_assoc=2
74224SN/A
751858SN/Aif args:
762518SN/A     print "Error: script doesn't take any positional arguments"
772420SN/A     sys.exit(1)
782519SN/A
792520SN/A#
802420SN/A# Create the ruby random tester
812SN/A#
822680Sktlim@umich.edu
832672Sktlim@umich.edu# Check the protocol
842680Sktlim@umich.educheck_flush = False
852SN/Aif buildEnv['PROTOCOL'] == 'MOESI_hammer':
862SN/A    check_flush = True
87334SN/A
88140SN/Atester = RubyTester(check_flush = check_flush,
89334SN/A                    checks_to_complete = options.checks,
902SN/A                    wakeup_frequency = options.wakeup_freq)
912SN/A
922SN/A#
932680Sktlim@umich.edu# Create the M5 system.  Note that the PhysicalMemory Object isn't
942SN/A# actually used by the rubytester, but is included to support the
952SN/A# M5 memory size == Ruby memory size checks
962623SN/A#
972SN/Asystem = System(tester = tester, physmem = PhysicalMemory())
982SN/A
992SN/ARuby.create_system(options, system)
100180SN/A
1012623SN/Aassert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
102393SN/A
103393SN/A#
104393SN/A# The tester is most effective when randomization is turned on and
105393SN/A# artifical delay is randomly inserted on messages
106384SN/A#
107384SN/Asystem.ruby.randomization = True
108393SN/A
1092623SN/Afor ruby_port in system.ruby._cpu_ruby_ports:
110393SN/A    #
111393SN/A    # Tie the ruby tester ports to the ruby cpu ports
112393SN/A    #
113393SN/A    tester.cpuPort = ruby_port.slave
114384SN/A
115189SN/A    #
116189SN/A    # Tell each sequencer this is the ruby tester so that it
1172623SN/A    # copies the subblock back to the checker
1182SN/A    #
119729SN/A    ruby_port.using_ruby_tester = True
120334SN/A
1212SN/A    #
1222SN/A    # Ruby doesn't need the backing image of memory when running with
1232SN/A    # the tester.
1242SN/A    #
1252SN/A    ruby_port.access_phys_mem = False
1262SN/A
1272SN/A# -----------------------
1282SN/A# run simulation
1292SN/A# -----------------------
1302SN/A
1312SN/Aroot = Root( full_system = False, system = system )
1322SN/Aroot.system.mem_mode = 'timing'
1331001SN/A
1341001SN/A# Not much point in this being higher than the L1 latency
1351001SN/Am5.ticks.setGlobalFrequency('1ns')
1361001SN/A
1371001SN/A# instantiate configuration
1382SN/Am5.instantiate()
1392SN/A
1402SN/A# simulate until program terminates
1412SN/Aexit_event = m5.simulate(options.maxtick)
1422SN/A
1432SN/Aprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
1442SN/A