ruby_random_test.py revision 8184
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
21762SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc.
32SN/A# All rights reserved.
42SN/A#
52SN/A# Redistribution and use in source and binary forms, with or without
62SN/A# modification, are permitted provided that the following conditions are
72SN/A# met: redistributions of source code must retain the above copyright
82SN/A# notice, this list of conditions and the following disclaimer;
92SN/A# redistributions in binary form must reproduce the above copyright
102SN/A# notice, this list of conditions and the following disclaimer in the
112SN/A# documentation and/or other materials provided with the distribution;
122SN/A# neither the name of the copyright holders nor the names of its
132SN/A# contributors may be used to endorse or promote products derived from
142SN/A# this software without specific prior written permission.
152SN/A#
162SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu#
282665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski
292665Ssaidi@eecs.umich.edu#          Brad Beckmann
302SN/A
312SN/Aimport m5
322SN/Afrom m5.objects import *
332SN/Afrom m5.defines import buildEnv
342SN/Afrom m5.util import addToPath
352SN/Aimport os, optparse, sys
361354SN/AaddToPath('../common')
371354SN/AaddToPath('../ruby')
382SN/A
392SN/Aimport Ruby
402SN/A
412SN/Aif buildEnv['FULL_SYSTEM']:
422SN/A    panic("This script requires system-emulation mode (*_SE).")
432SN/A
442SN/A# Get paths we might need.  It's expected this file is in m5/configs/example.
452SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__))
4656SN/Aconfig_root = os.path.dirname(config_path)
472SN/Am5_root = os.path.dirname(config_root)
4856SN/A
492361SN/Aparser = optparse.OptionParser()
501354SN/A
5156SN/Aparser.add_option("-l", "--checks", metavar="N", default=100,
522SN/A                  help="Stop after N checks (loads)")
532SN/Aparser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
542SN/A                  help="Wakeup every N cycles")
551354SN/A
561354SN/A#
571354SN/A# Add the ruby specific and protocol specific options
581354SN/A#
591354SN/ARuby.define_options(parser)
601354SN/A
611354SN/Aexecfile(os.path.join(config_root, "common", "Options.py"))
621354SN/A
631354SN/A(options, args) = parser.parse_args()
641354SN/A
651354SN/A#
661354SN/A# Set the default cache size and associativity to be very small to encourage
671354SN/A# races between requests and writebacks.
682SN/A#
692SN/Aoptions.l1d_size="256B"
702SN/Aoptions.l1i_size="256B"
712SN/Aoptions.l2_size="512B"
722SN/Aoptions.l3_size="1kB"
73395SN/Aoptions.l1d_assoc=2
742SN/Aoptions.l1i_assoc=2
752SN/Aoptions.l2_assoc=2
762SN/Aoptions.l3_assoc=2
772SN/A
782SN/Aif args:
792SN/A     print "Error: script doesn't take any positional arguments"
802SN/A     sys.exit(1)
812SN/A
822SN/A#
832SN/A# Create the ruby random tester
842SN/A#
852SN/A
862SN/A# Check the protocol
872SN/Acheck_flush = False
882SN/Aif buildEnv['PROTOCOL'] == 'MOESI_hammer':
892SN/A    check_flush = True
902SN/A
912SN/Atester = RubyTester(check_flush = check_flush,
922SN/A                    checks_to_complete = options.checks,
93237SN/A                    wakeup_frequency = options.wakeup_freq)
942667Sstever@eecs.umich.edu
952667Sstever@eecs.umich.edu#
962SN/A# Create the M5 system.  Note that the PhysicalMemory Object isn't
972SN/A# actually used by the rubytester, but is included to support the
982SN/A# M5 memory size == Ruby memory size checks
992SN/A#
1002SN/Asystem = System(tester = tester, physmem = PhysicalMemory())
1012SN/A
1022SN/Asystem.ruby = Ruby.create_system(options, system)
1032SN/A
1042SN/Aassert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
1052SN/A
1062SN/A#
1072SN/A# The tester is most effective when randomization is turned on and
1082SN/A# artifical delay is randomly inserted on messages
1092SN/A#
1102SN/Asystem.ruby.randomization = True
1112SN/A
1122SN/Afor ruby_port in system.ruby.cpu_ruby_ports:
1132SN/A    #
1142SN/A    # Tie the ruby tester ports to the ruby cpu ports
1152SN/A    #
1162SN/A    tester.cpuPort = ruby_port.port
1172SN/A
118396SN/A    #
119396SN/A    # Tell each sequencer this is the ruby tester so that it
120396SN/A    # copies the subblock back to the checker
121396SN/A    #
122396SN/A    ruby_port.using_ruby_tester = True
1233329Sstever@eecs.umich.edu
1243329Sstever@eecs.umich.edu# -----------------------
1253329Sstever@eecs.umich.edu# run simulation
1263329Sstever@eecs.umich.edu# -----------------------
1273329Sstever@eecs.umich.edu
1283329Sstever@eecs.umich.eduroot = Root( system = system )
1293329Sstever@eecs.umich.eduroot.system.mem_mode = 'timing'
1303329Sstever@eecs.umich.edu
131396SN/A# Not much point in this being higher than the L1 latency
132396SN/Am5.ticks.setGlobalFrequency('1ns')
1333329Sstever@eecs.umich.edu
1343329Sstever@eecs.umich.edu# instantiate configuration
1353329Sstever@eecs.umich.edum5.instantiate()
1363329Sstever@eecs.umich.edu
1373329Sstever@eecs.umich.edu# simulate until program terminates
1383329Sstever@eecs.umich.eduexit_event = m5.simulate(options.maxtick)
139396SN/A
140396SN/Aprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
141396SN/A