ruby_random_test.py revision 8184
111264Sandreas.sandberg@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 211264Sandreas.sandberg@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 311264Sandreas.sandberg@arm.com# All rights reserved. 411264Sandreas.sandberg@arm.com# 511264Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 611264Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are 711264Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright 811264Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer; 911264Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright 1011264Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 1111264Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution; 1211264Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its 1311264Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from 1411264Sandreas.sandberg@arm.com# this software without specific prior written permission. 1511264Sandreas.sandberg@arm.com# 1611264Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711264Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811264Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911264Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011264Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111264Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211264Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311264Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411264Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511264Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611264Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711264Sandreas.sandberg@arm.com# 2811264Sandreas.sandberg@arm.com# Authors: Ron Dreslinski 2911264Sandreas.sandberg@arm.com# Brad Beckmann 3011264Sandreas.sandberg@arm.com 3111264Sandreas.sandberg@arm.comimport m5 3211264Sandreas.sandberg@arm.comfrom m5.objects import * 3311264Sandreas.sandberg@arm.comfrom m5.defines import buildEnv 3411264Sandreas.sandberg@arm.comfrom m5.util import addToPath 3511264Sandreas.sandberg@arm.comimport os, optparse, sys 3611264Sandreas.sandberg@arm.comaddToPath('../common') 3711264Sandreas.sandberg@arm.comaddToPath('../ruby') 3811264Sandreas.sandberg@arm.com 3911264Sandreas.sandberg@arm.comimport Ruby 4011264Sandreas.sandberg@arm.com 4111264Sandreas.sandberg@arm.comif buildEnv['FULL_SYSTEM']: 4211264Sandreas.sandberg@arm.com panic("This script requires system-emulation mode (*_SE).") 4311264Sandreas.sandberg@arm.com 4411264Sandreas.sandberg@arm.com# Get paths we might need. It's expected this file is in m5/configs/example. 4511264Sandreas.sandberg@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 4611264Sandreas.sandberg@arm.comconfig_root = os.path.dirname(config_path) 4711264Sandreas.sandberg@arm.comm5_root = os.path.dirname(config_root) 4811264Sandreas.sandberg@arm.com 4911264Sandreas.sandberg@arm.comparser = optparse.OptionParser() 5011264Sandreas.sandberg@arm.com 5111264Sandreas.sandberg@arm.comparser.add_option("-l", "--checks", metavar="N", default=100, 5211264Sandreas.sandberg@arm.com help="Stop after N checks (loads)") 5311264Sandreas.sandberg@arm.comparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 5411264Sandreas.sandberg@arm.com help="Wakeup every N cycles") 5511264Sandreas.sandberg@arm.com 5611264Sandreas.sandberg@arm.com# 5711264Sandreas.sandberg@arm.com# Add the ruby specific and protocol specific options 5811264Sandreas.sandberg@arm.com# 5911264Sandreas.sandberg@arm.comRuby.define_options(parser) 6011264Sandreas.sandberg@arm.com 6111264Sandreas.sandberg@arm.comexecfile(os.path.join(config_root, "common", "Options.py")) 6211264Sandreas.sandberg@arm.com 6311264Sandreas.sandberg@arm.com(options, args) = parser.parse_args() 6411264Sandreas.sandberg@arm.com 6511264Sandreas.sandberg@arm.com# 6611264Sandreas.sandberg@arm.com# Set the default cache size and associativity to be very small to encourage 6711264Sandreas.sandberg@arm.com# races between requests and writebacks. 6811264Sandreas.sandberg@arm.com# 6911264Sandreas.sandberg@arm.comoptions.l1d_size="256B" 7011264Sandreas.sandberg@arm.comoptions.l1i_size="256B" 7111264Sandreas.sandberg@arm.comoptions.l2_size="512B" 7211264Sandreas.sandberg@arm.comoptions.l3_size="1kB" 7311264Sandreas.sandberg@arm.comoptions.l1d_assoc=2 74options.l1i_assoc=2 75options.l2_assoc=2 76options.l3_assoc=2 77 78if args: 79 print "Error: script doesn't take any positional arguments" 80 sys.exit(1) 81 82# 83# Create the ruby random tester 84# 85 86# Check the protocol 87check_flush = False 88if buildEnv['PROTOCOL'] == 'MOESI_hammer': 89 check_flush = True 90 91tester = RubyTester(check_flush = check_flush, 92 checks_to_complete = options.checks, 93 wakeup_frequency = options.wakeup_freq) 94 95# 96# Create the M5 system. Note that the PhysicalMemory Object isn't 97# actually used by the rubytester, but is included to support the 98# M5 memory size == Ruby memory size checks 99# 100system = System(tester = tester, physmem = PhysicalMemory()) 101 102system.ruby = Ruby.create_system(options, system) 103 104assert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) 105 106# 107# The tester is most effective when randomization is turned on and 108# artifical delay is randomly inserted on messages 109# 110system.ruby.randomization = True 111 112for ruby_port in system.ruby.cpu_ruby_ports: 113 # 114 # Tie the ruby tester ports to the ruby cpu ports 115 # 116 tester.cpuPort = ruby_port.port 117 118 # 119 # Tell each sequencer this is the ruby tester so that it 120 # copies the subblock back to the checker 121 # 122 ruby_port.using_ruby_tester = True 123 124# ----------------------- 125# run simulation 126# ----------------------- 127 128root = Root( system = system ) 129root.system.mem_mode = 'timing' 130 131# Not much point in this being higher than the L1 latency 132m5.ticks.setGlobalFrequency('1ns') 133 134# instantiate configuration 135m5.instantiate() 136 137# simulate until program terminates 138exit_event = m5.simulate(options.maxtick) 139 140print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 141