ruby_mem_test.py revision 7938:685719afafe6
15353Svilas.sridharan@gmail.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 23395Shsul@eecs.umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 33395Shsul@eecs.umich.edu# All rights reserved. 43395Shsul@eecs.umich.edu# 53395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 73395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143395Shsul@eecs.umich.edu# this software without specific prior written permission. 153395Shsul@eecs.umich.edu# 163395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# Authors: Ron Dreslinski 298920Snilay@cs.wisc.edu# Brad Beckmann 308920Snilay@cs.wisc.edu 318920Snilay@cs.wisc.eduimport m5 328920Snilay@cs.wisc.edufrom m5.objects import * 337025SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 348920Snilay@cs.wisc.edufrom m5.util import addToPath 358920Snilay@cs.wisc.eduimport os, optparse, sys 368920Snilay@cs.wisc.eduaddToPath('../common') 378920Snilay@cs.wisc.eduaddToPath('../ruby') 388920Snilay@cs.wisc.edu 398920Snilay@cs.wisc.eduimport Ruby 408920Snilay@cs.wisc.edu 418920Snilay@cs.wisc.eduif buildEnv['FULL_SYSTEM']: 428920Snilay@cs.wisc.edu panic("This script requires system-emulation mode (*_SE).") 438920Snilay@cs.wisc.edu 448920Snilay@cs.wisc.edu# Get paths we might need. It's expected this file is in m5/configs/example. 458920Snilay@cs.wisc.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 468920Snilay@cs.wisc.educonfig_root = os.path.dirname(config_path) 478920Snilay@cs.wisc.edum5_root = os.path.dirname(config_root) 488920Snilay@cs.wisc.edu 498920Snilay@cs.wisc.eduparser = optparse.OptionParser() 508920Snilay@cs.wisc.edu 518920Snilay@cs.wisc.eduparser.add_option("-l", "--maxloads", metavar="N", default=0, 528920Snilay@cs.wisc.edu help="Stop after N loads") 538920Snilay@cs.wisc.eduparser.add_option("--progress", type="int", default=1000, 548920Snilay@cs.wisc.edu metavar="NLOADS", 558920Snilay@cs.wisc.edu help="Progress message interval " 568920Snilay@cs.wisc.edu "[default: %default]") 578920Snilay@cs.wisc.eduparser.add_option("--num-dmas", type="int", default=0, help="# of dma testers") 588920Snilay@cs.wisc.edu 593395Shsul@eecs.umich.edu# 608920Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 618920Snilay@cs.wisc.edu# 628920Snilay@cs.wisc.eduRuby.define_options(parser) 638920Snilay@cs.wisc.edu 648920Snilay@cs.wisc.eduexecfile(os.path.join(config_root, "common", "Options.py")) 658920Snilay@cs.wisc.edu 668920Snilay@cs.wisc.edu(options, args) = parser.parse_args() 678920Snilay@cs.wisc.edu 688920Snilay@cs.wisc.edu# 698920Snilay@cs.wisc.edu# Set the default cache size and associativity to be very small to encourage 708920Snilay@cs.wisc.edu# races between requests and writebacks. 718920Snilay@cs.wisc.edu# 728920Snilay@cs.wisc.eduoptions.l1d_size="256B" 738920Snilay@cs.wisc.eduoptions.l1i_size="256B" 748920Snilay@cs.wisc.eduoptions.l2_size="512B" 758920Snilay@cs.wisc.eduoptions.l3_size="1kB" 768920Snilay@cs.wisc.eduoptions.l1d_assoc=2 778920Snilay@cs.wisc.eduoptions.l1i_assoc=2 786776SBrad.Beckmann@amd.comoptions.l2_assoc=2 798920Snilay@cs.wisc.eduoptions.l3_assoc=2 808920Snilay@cs.wisc.edu 818920Snilay@cs.wisc.eduif args: 828920Snilay@cs.wisc.edu print "Error: script doesn't take any positional arguments" 838920Snilay@cs.wisc.edu sys.exit(1) 848920Snilay@cs.wisc.edu 858920Snilay@cs.wisc.edublock_size = 64 868920Snilay@cs.wisc.edu 878920Snilay@cs.wisc.eduif options.num_cpus > block_size: 888920Snilay@cs.wisc.edu print "Error: Number of testers %d limited to %d because of false sharing" \ 898920Snilay@cs.wisc.edu % (options.num_cpus, block_size) 908920Snilay@cs.wisc.edu sys.exit(1) 918920Snilay@cs.wisc.edu 928920Snilay@cs.wisc.edu# 938920Snilay@cs.wisc.edu# Currently ruby does not support atomic, functional, or uncacheable accesses 948920Snilay@cs.wisc.edu# 958920Snilay@cs.wisc.educpus = [ MemTest(atomic = False, \ 968920Snilay@cs.wisc.edu max_loads = options.maxloads, \ 978920Snilay@cs.wisc.edu issue_dmas = False, \ 988920Snilay@cs.wisc.edu percent_functional = 0, \ 998920Snilay@cs.wisc.edu percent_uncacheable = 0, \ 1008920Snilay@cs.wisc.edu progress_interval = options.progress) \ 1018920Snilay@cs.wisc.edu for i in xrange(options.num_cpus) ] 1023395Shsul@eecs.umich.edu 1035361Srstrong@cs.ucsd.edusystem = System(cpu = cpus, 1048920Snilay@cs.wisc.edu funcmem = PhysicalMemory(), 1058920Snilay@cs.wisc.edu physmem = PhysicalMemory()) 1068920Snilay@cs.wisc.edu 1078920Snilay@cs.wisc.eduif options.num_dmas > 0: 1088920Snilay@cs.wisc.edu dmas = [ MemTest(atomic = False, \ 1098920Snilay@cs.wisc.edu max_loads = options.maxloads, \ 1108920Snilay@cs.wisc.edu issue_dmas = True, \ 1118920Snilay@cs.wisc.edu percent_functional = 0, \ 1128920Snilay@cs.wisc.edu percent_uncacheable = 0, \ 1138920Snilay@cs.wisc.edu progress_interval = options.progress) \ 1148920Snilay@cs.wisc.edu for i in xrange(options.num_dmas) ] 1158920Snilay@cs.wisc.edu system.dma_devices = dmas 1168920Snilay@cs.wisc.eduelse: 1178920Snilay@cs.wisc.edu dmas = [] 1188920Snilay@cs.wisc.edu 1198920Snilay@cs.wisc.edusystem.ruby = Ruby.create_system(options, \ 1208920Snilay@cs.wisc.edu system, \ 1218920Snilay@cs.wisc.edu dma_devices = dmas) 1228920Snilay@cs.wisc.edu 1238920Snilay@cs.wisc.edu# 1248920Snilay@cs.wisc.edu# The tester is most effective when randomization is turned on and 1258920Snilay@cs.wisc.edu# artifical delay is randomly inserted on messages 1268920Snilay@cs.wisc.edu# 1278920Snilay@cs.wisc.edusystem.ruby.randomization = True 1288920Snilay@cs.wisc.edu 1298920Snilay@cs.wisc.eduassert(len(cpus) == len(system.ruby.cpu_ruby_ports)) 1308920Snilay@cs.wisc.edu 1318920Snilay@cs.wisc.edufor (i, cpu) in enumerate(cpus): 1328920Snilay@cs.wisc.edu # 1338920Snilay@cs.wisc.edu # Tie the cpu memtester ports to the correct system ports 1348920Snilay@cs.wisc.edu # 1358920Snilay@cs.wisc.edu cpu.test = system.ruby.cpu_ruby_ports[i].port 1368920Snilay@cs.wisc.edu cpu.functional = system.funcmem.port 1378920Snilay@cs.wisc.edu 1388920Snilay@cs.wisc.edu # 1398920Snilay@cs.wisc.edu # Since the memtester is incredibly bursty, increase the deadlock 1408920Snilay@cs.wisc.edu # threshold to 5 million cycles 1418920Snilay@cs.wisc.edu # 1428920Snilay@cs.wisc.edu system.ruby.cpu_ruby_ports[i].deadlock_threshold = 5000000 1438920Snilay@cs.wisc.edu 1448920Snilay@cs.wisc.edufor (i, dma) in enumerate(dmas): 1458920Snilay@cs.wisc.edu # 1468920Snilay@cs.wisc.edu # Tie the dma memtester ports to the correct functional port 1478920Snilay@cs.wisc.edu # Note that the test port has already been connected to the dma_sequencer 1488920Snilay@cs.wisc.edu # 1498920Snilay@cs.wisc.edu dma.functional = system.funcmem.port 1508920Snilay@cs.wisc.edu 1518920Snilay@cs.wisc.edu# ----------------------- 1528920Snilay@cs.wisc.edu# run simulation 1538920Snilay@cs.wisc.edu# ----------------------- 1548920Snilay@cs.wisc.edu 1558920Snilay@cs.wisc.eduroot = Root( system = system ) 1568920Snilay@cs.wisc.eduroot.system.mem_mode = 'timing' 1578920Snilay@cs.wisc.edu 1588920Snilay@cs.wisc.edu# Not much point in this being higher than the L1 latency 1598920Snilay@cs.wisc.edum5.ticks.setGlobalFrequency('1ns') 1608920Snilay@cs.wisc.edu 1618920Snilay@cs.wisc.edu# instantiate configuration 1628920Snilay@cs.wisc.edum5.instantiate() 1638920Snilay@cs.wisc.edu 1648920Snilay@cs.wisc.edu# simulate until program terminates 1658920Snilay@cs.wisc.eduexit_event = m5.simulate(options.maxtick) 1668920Snilay@cs.wisc.edu 1678920Snilay@cs.wisc.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 1688920Snilay@cs.wisc.edu